Variational delay metrics for interconnect timing analysis

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Variational delay metrics for interconnect timing analysis

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 41st annual Design Automation Conference table of contents

San Diego, CA, USA

SESSION: Model order reduction and variational techniques for parasitic analysis table of contents

Pages: 381 - 384

Year of Publication: 2004

ISBN:1-58113-828-8

Authors

Kanak Agarwal	University of Michigan, Ann Arbor, MI
Dennis Sylvester	University of Michigan, Ann Arbor, MI
David Blaauw	University of Michigan, Ann Arbor, MI
Frank Liu	IBM Research, Austin, TX
Sani Nassif	IBM Research, Austin, TX
Sarma Vrudhula	University of Arizona, Tucson, AZ

Sponsors

ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation

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ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 8, Downloads (12 Months): 42, Citation Count: 29

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abstract references cited by index terms collaborative colleagues

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ABSTRACT

In this paper we develop an approach to model interconnect delay under process variability for timing analysis and physical design optimization. The technique allows for closed-form computation of interconnect delay probability density functions (PDFs) given variations in relevant process parameters such as linewidth, metal thickness, and dielectric thickness. We express the resistance and capacitance of a line as a linear function of random variables and then use these to compute circuit moments. Finally, these variability-aware moments are used in known closed-form delay metrics to compute interconnect delay PDFs. We compare the approach to SPICE based Monte Carlo simulations and report an error in mean and standard deviation of delay of 1% and 4% on average, respectively.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	S. R. Nassif, "Modeling and Analysis of Manufacturing Variations," CICC, pp. 223--228, 2001.
	2	Z. Lin, C. Spanos, L. Milor, and Y. Lin, "Circuit Sensitivity to Interconnect Variation," IEEE Trans. on Semiconductor Manufacturing, v. 11, pp. 557--568, Nov. 1998.
	3	Ying Liu , Sani R. Nassif , Lawrence T. Pileggi , Andrzej J. Strojwas, Impact of interconnect variations on the clock skew of a gigahertz microprocessor, Proceedings of the 37th conference on Design automation, p.168-171, June 05-09, 2000, Los Angeles, California, United States [doi>10.1145/337292.337365]
	4	Ying Liu , Lawrence T. Pileggi , Andrzej J. Strojwas, Model order-reduction of RC(L) interconnect including variational analysis, Proceedings of the 36th ACM/IEEE conference on Design automation, p.201-206, June 21-25, 1999, New Orleans, Louisiana, United States [doi>10.1145/309847.309914]
	5	Altan Odabasioglu , Mustafa Celik , Lawrence T. Pileggi, PRIMA: passive reduced-order interconnect macromodeling algorithm, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.58-65, November 09-13, 1997, San Jose, California, United States
	6	Curtis L. Ratzlaff , Nanda Gopal , Lawrence T. Pillage, RICE: Rapid interconnect circuit evaluator, Proceedings of the 28th conference on ACM/IEEE design automation, p.555-560, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127732]
	7	W.C. Elmore, "The transient response of damped linear networks with particular regard to wideband amplifiers," J. Applied Physics, v. 19, pp. 55--63, Jan. 1948.
	8	Charles J. Alpert , Anirudh Devgan , Chandramouli Kashyap, A two moment RC delay metric for performance optimization, Proceedings of the 2000 international symposium on Physical design, p.69-74, May 2000, San Diego, California, United States [doi>10.1145/332357.332377]
	9	Kanak Agarwal , Dennis Sylvester , David Blaauw, Simple metrics for slew rate of RC circuits based on two circuit moments, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA [doi>10.1145/775832.776070]
	10	Frank Liu , Chandramouli Kashyap , Charles J. Alpert, A delay metric for RC circuits based on the Weibull distribution, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.620-624, November 10-14, 2002, San Jose, California [doi>10.1145/774572.774664]
	11	Tao Lin , Emrah Acar , Lawrence Pileggi, h-gamma: an RC delay metric based on a gamma distribution approximation of the homogeneous response, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.19-25, November 08-12, 1998, San Jose, California, United States [doi>10.1145/288548.288555]
	12	V. Mehrotra, S. Nassif, D. Boning, and J. Chung, "Modeling the Effects of Manufacturing Variation on High-Speed Microprocessor Interconnect Performance," IEEE Electron Devices Meetings, pp. 767--770, 1998.
	13	J. Chern, J. Huang, L. Arledge, P. Li, and P. Yang, "Multilevel Metal Capacitance Models for CAD Design Synthesis Systems," IEEE Electron Devices Letters, pp. 32--34, Jan. 1992.

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	Matthew R. Guthaus , Dennis Sylvester , Richard B. Brown, Process-induced skew reduction in nominal zero-skew clock trees, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
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