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Placement feedback: a concept and method for better min-cut placements
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 41st annual Design Automation Conference table of contents
San Diego, CA, USA
SESSION: New ideas in placement table of contents
Pages: 357 - 362  
Year of Publication: 2004
ISBN:1-58113-828-8
Authors
Andrew B. Kahng  University of CA, La Jolla, CA
Sherief Reda  University of CA, La Jolla, CA
Sponsors
ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 2,   Downloads (12 Months): 14,   Citation Count: 10
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ABSTRACT

The advent of strong multi-level partitioners has made topdown min-cut placers a favored choice for modern placer implementations. We examine terminal propagation, an important step in min-cut placers, because it is responsible for translating partitioning results into global placement wirelength assumptions. In this work, we identify a previously overlooked problem - ambiguous terminal propagation - and propose a solution based on the concept of feedback from automatic control systems. Implementing our approach in Capo (version 8.7 [5, 10]) and applying it to standard benchmark circuits yields up to 14% wirelength reductions for the IBM benchmarks and 10% reductions for PEKO instances. Experiments also show consistent improvements for routed wirelength, yielding up to 9% wirelength reductions with practical increase in placement runtime. In addition, our method significantly improves routability without building congestion maps, and reduces the number of vias.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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A. E. Caldwell, A. B. Kahng and I. L. Markov, "Optimal Partitioners and End-case Placers for Standard-cell Layout," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 19(11), 2000, pp. 1304--1313.
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A. E. Dunlop and B. W. Kernighan, "A Procedure for Placement of Standard-Cell VLSI Circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 4(1), 1985, pp. 92--98.
 
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I. L. Markov, Private communication, November 2003.
 
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P. R. Suaris and G. Kedem, "A Quadrisection-Based Combined Place and Route Scheme for Standard Cells," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 8(3), 1989, pp. 234--244.
 
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CITED BY  10

Collaborative Colleagues:
Andrew B. Kahng: colleagues
Sherief Reda: colleagues