| Placement feedback: a concept and method for better min-cut placements |
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Annual ACM IEEE Design Automation Conference
archive
Proceedings of the 41st annual Design Automation Conference
table of contents
San Diego, CA, USA
SESSION: New ideas in placement
table of contents
Pages: 357 - 362
Year of Publication: 2004
ISBN:1-58113-828-8
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Downloads (6 Weeks): 2, Downloads (12 Months): 14, Citation Count: 10
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ABSTRACT
The advent of strong multi-level partitioners has made topdown min-cut placers a favored choice for modern placer implementations. We examine terminal propagation, an important step in min-cut placers, because it is responsible for translating partitioning results into global placement wirelength assumptions. In this work, we identify a previously overlooked problem - ambiguous terminal propagation - and propose a solution based on the concept of feedback from automatic control systems. Implementing our approach in Capo (version 8.7 [5, 10]) and applying it to standard benchmark circuits yields up to 14% wirelength reductions for the IBM benchmarks and 10% reductions for PEKO instances. Experiments also show consistent improvements for routed wirelength, yielding up to 9% wirelength reductions with practical increase in placement runtime. In addition, our method significantly improves routability without building congestion maps, and reduces the number of vias.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Ameya Agnihotri , Mehmet Can YILDIZ , Ateen Khatkhate , Ajita Mathur , Satoshi Ono , Patrick H. Madden, Fractional Cut: Improved Recursive Bisection Placement, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.307, November 09-13, 2003
[doi> 10.1109/ICCAD.2003.72]
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Charles J. Alpert , Jen-Hsin Huang , Andrew B. Kahng, Multilevel circuit partitioning, Proceedings of the 34th annual conference on Design automation, p.530-533, June 09-13, 1997, Anaheim, California, United States
[doi> 10.1145/266021.266275]
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A. E. Caldwell , A. B. Kahng , I. L. Markov, Optimal partitioners and end-case placers for standard-cell layout, Proceedings of the 1999 international symposium on Physical design, p.90-96, April 12-14, 1999, Monterey, California, United States
[doi> 10.1145/299996.300032]
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Andrew E. Caldwell , Andrew B. Kahng , Igor L. Markov, Can recursive bisection alone produce routable placements?, Proceedings of the 37th conference on Design automation, p.477-482, June 05-09, 2000, Los Angeles, California, United States
[doi> 10.1145/337292.337549]
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A. E. Caldwell, A. B. Kahng and I. L. Markov, "Optimal Partitioners and End-case Placers for Standard-cell Layout," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 19(11), 2000, pp. 1304--1313.
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A. E. Dunlop and B. W. Kernighan, "A Procedure for Placement of Standard-Cell VLSI Circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 4(1), 1985, pp. 92--98.
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I. L. Markov, Private communication, November 2003.
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P. R. Suaris and G. Kedem, "A Quadrisection-Based Combined Place and Route Scheme for Standard Cells," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 8(3), 1989, pp. 234--244.
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CITED BY 10
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Jarrod A. Roy , David A. Papa , Saurabh N. Adya , Hayward H. Chan , Aaron N. Ng , James F. Lu , Igor L. Markov, Capo: robust and scalable open-source min-cut floorplacer, Proceedings of the 2005 international symposium on Physical design, April 03-06, 2005, San Francisco, California, USA
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Jarrod A. Roy , David A. Papa , Aaron N. Ng , Igor L. Markov, Satisfying whitespace requirements in top-down placement, Proceedings of the 2006 international symposium on Physical design, April 09-12, 2006, San Jose, California, USA
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S. N. Adya , S. Chaturvedi , J. A. Roy , D. A. Papa , I. L. Markov, Unification of partitioning, placement and floorplanning, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.550-557, November 07-11, 2004
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