First-order incremental block-based statistical timing analysis

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First-order incremental block-based statistical timing analysis

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 41st annual Design Automation Conference table of contents

San Diego, CA, USA

SESSION: Statistical timing analysis table of contents

Pages: 331 - 336

Year of Publication: 2004

ISBN:1-58113-828-8

Authors

C. Visweswariah	T. J. Watson Research Center, Yorktown Heights, NY
K. Ravindran	University of California, Berkeley, CA
K. Kalafala	IBM Microelectronics, East Fishkill, NY & Burlington, VT
S. G. Walker	T. J. Watson Research Center, Yorktown Heights, NY
S. Narayan	IBM Microelectronics, East Fishkill, NY & Burlington, VT

Sponsors

ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation

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ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 27, Downloads (12 Months): 107, Citation Count: 139

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ABSTRACT

Variability in digital integrated circuits makes timing verification an extremely challenging task. In this paper, a canonical first order delay model is proposed that takes into account both correlated and independent randomness. A novel linear-time block-based statistical timing algorithm is employed to propagate timing quantities like arrival times and required arrival times through the timing graph in this canonical form. At the end of the statistical timing, the sensitivities of all timing quantities to each of the sources of variation are available. Excessive sensitivities can then be targeted by manual or automatic optimization methods to improve the robustness of the design. This paper also reports the first incremental statistical timer in the literature which is suitable for use in the inner loop of physical synthesis or other optimization programs. The third novel contribution of this paper is the computation of local and global criticality probabilities. For a very small cost in CPU time, the probability of each edge or node of the timing graph being critical is computed. Numerical results are presented on industrial ASIC chips with over two million logic gates.

REFERENCES

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