| Circuit-aware architectural simulation |
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Annual ACM IEEE Design Automation Conference
archive
Proceedings of the 41st annual Design Automation Conference
table of contents
San Diego, CA, USA
SESSION: Advances in accelerated simulation
table of contents
Pages: 305 - 310
Year of Publication: 2004
ISBN:1-58113-828-8
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Authors
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Seokwoo Lee
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The University of Michigan, Ann Arbor, MI
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Shidhartha Das
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The University of Michigan, Ann Arbor, MI
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Valeria Bertacco
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The University of Michigan, Ann Arbor, MI
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Todd Austin
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The University of Michigan, Ann Arbor, MI
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David Blaauw
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The University of Michigan, Ann Arbor, MI
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Trevor Mudge
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The University of Michigan, Ann Arbor, MI
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| Bibliometrics |
Downloads (6 Weeks): 4, Downloads (12 Months): 25, Citation Count: 3
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ABSTRACT
Architectural simulation has achieved a prominent role in the system design cycle by providing designers the ability to quickly examine a wide variety of design choices. However, the recent trend in system design toward architectures that react to circuit-level phenomena has outstripped the capabilities of traditional cycle-based architectural simulators. In this paper, we present an architectural simulator design that incorporates a circuit modeling capability, permitting architectural-level simulations that react to circuit characteristics (such as latency,energy,or current draw) on a cycle-by-cycle basis. While these additional capabilities slow simulation speed, we show that the careful application of circuit simulation optimizations and simulation sampling techniques permit high levels of detail with sufficient speed to examine entire workloads.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Dan Ernst , Nam Sung Kim , Shidhartha Das , Sanjay Pant , Rajeev Rao , Toan Pham , Conrad Ziesler , David Blaauw , Todd Austin , Krisztian Flautner , Trevor Mudge, Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation, Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture, p.7, December 03-05, 2003
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[doi> 10.1145/127601.127732]
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CITED BY 3
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Dan Ernst , Shidhartha Das , Seokwoo Lee , David Blaauw , Todd Austin , Trevor Mudge , Nam Sung Kim , Krisztian Flautner, Razor: Circuit-Level Correction of Timing Errors for Low-Power Operation, IEEE Micro, v.24 n.6, p.10-20, November 2004
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Seokwoo Lee , Shidhartha Das , Toan Pham , Todd Austin , David Blaauw , Trevor Mudge, Reducing pipeline energy demands with local DVS and dynamic retiming, Proceedings of the 2004 international symposium on Low power electronics and design, August 09-11, 2004, Newport Beach, California, USA
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