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Circuit-aware architectural simulation
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 41st annual Design Automation Conference table of contents
San Diego, CA, USA
SESSION: Advances in accelerated simulation table of contents
Pages: 305 - 310  
Year of Publication: 2004
ISBN:1-58113-828-8
Authors
Seokwoo Lee  The University of Michigan, Ann Arbor, MI
Shidhartha Das  The University of Michigan, Ann Arbor, MI
Valeria Bertacco  The University of Michigan, Ann Arbor, MI
Todd Austin  The University of Michigan, Ann Arbor, MI
David Blaauw  The University of Michigan, Ann Arbor, MI
Trevor Mudge  The University of Michigan, Ann Arbor, MI
Sponsors
ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 4,   Downloads (12 Months): 25,   Citation Count: 3
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ABSTRACT

Architectural simulation has achieved a prominent role in the system design cycle by providing designers the ability to quickly examine a wide variety of design choices. However, the recent trend in system design toward architectures that react to circuit-level phenomena has outstripped the capabilities of traditional cycle-based architectural simulators. In this paper, we present an architectural simulator design that incorporates a circuit modeling capability, permitting architectural-level simulations that react to circuit characteristics (such as latency,energy,or current draw) on a cycle-by-cycle basis. While these additional capabilities slow simulation speed, we show that the careful application of circuit simulation optimizations and simulation sampling techniques permit high levels of detail with sufficient speed to examine entire workloads.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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E. Acuna, J. Dervenis, A. Pagones, and R. Saleh. iSPLICE3: a new simulator for mixed analog/digital circuits. In IEEE Custom Integrated Circuits Conference, pages 13.1/1--13.1/4, May 1989.
 
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G. Cai and C. H. Lim. Architectural level power/performance optimization and dynamic power estimation. In Cool Chips Tutorial in conjunction with the 32nd Int. Symp. on Microarchitecture (MICRO-32), Nov. 1999.
 
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B. Calder. Simpoint website. In http://www.cse.ucsd.edu/ calder/simpoint/, 2003.
 
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C. Visweswariah and R. Rohrer. SPECS2: An integrated circuit timing simulator. In ICCAD, Proceedings of the International Conference on Computer Aided Design, pages 94--97, Nov. 1987.
 
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S. Wilton and N. Jouppi. An enhanced access and cycle time model for on-chip caches. In Western Research Laboratory Research Report 93/5, July 1993.


Collaborative Colleagues:
Seokwoo Lee: colleagues
Shidhartha Das: colleagues
Valeria Bertacco: colleagues
Todd Austin: colleagues
David Blaauw: colleagues
Trevor Mudge: colleagues