A fast hardware/software co-verification method for system-on-a-chip by using a C/C++ simulator and FPGA emulator with shared register communication

ABSTRACT

This paper describes a new hardware/software co-verification method for System-On-a-Chip, based on the integration of a C/C++ simulator and an inexpensive FPGA emulator. Communication between the simulator and emulator occurs via a flexible interface based on shared communication registers. This method enables easy debugging, rich portability, and high verification speed, at a low cost. We describe the application of this environment to the verification of three different complex commercial SoCs, supporting concurrent hardware and embedded software development. In these projects, our verification methodology was used to perform complete system verification at 0.2-1.1 MHz, while supporting full graphical interface functions such as "waveform" or "signal dump" viewers, and debugging functions such as "step" or "break".

REFERENCES

• 1: Roger Lipsett , Cary A. Ussery , Carl F. Schaefer, VHDL, Hardware Description and Design, Kluwer Academic Publishers, Norwell, MA, 1993
• 2: Donald E. Thomas , Philip R. Moorby, The VERILOG Hardware Description Language, Kluwer Academic Publishers, Norwell, MA, 1991
• 3: D. D. Gajski, et al, "SPEC C: Specification Language and Methodology", Kluwer Academic Publishers, 2000.
• 4: System C, "http://www.systemc.org"
• 5: James Gateley , Miriam Blatt , Dennis Chen , Scott Cooke , Piyush Desai , Manjunath Doreswamy , Mark Elgood , Gary Feierbach , Tim Goldsbury , Dale Greenley, UltraSPARC-I, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.13-18, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217483]
• 6: Françoise Casaubieilh , Anthony McIsaac , Mike Benjamin , Mike Bartley , François Pogodalla , Frédéric Rocheteau , Mohamed Belhadj , Jeremy Eggleton , Gérard Mas , Geoff Barrett , Christian Berthet, Functional verification methodology of Chameleon processor, Proceedings of the 33rd annual conference on Design automation, p.421-426, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240599]
• 7: Gopi Ganapathy , Ram Narayan , Glenn Jorden , Denzil Fernandez , Ming Wang , Jim Nishimura, Hardware emulation for functional verification of K5, Proceedings of the 33rd annual conference on Design automation, p.315-318, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240578]
• 8: James Monaco , David Holloway , Rajesh Raina, Functional verification methodology for the PowerPC 604 microprocessor, Proceedings of the 33rd annual conference on Design automation, p.319-324, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240579]
• 9: Namseung Kim , Hoon Choi , Seungjong Lee , Seungwang Lee , In-Cheolo Park , Chong-Min Kyung, Virtual chip: making functional models work on real target systems, Proceedings of the 35th annual conference on Design automation, p.170-173, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277084]
• 10: Murali Kudlugi , Soha Hassoun , Charles Selvidge , Duaine Pryor, A transaction-based unified simulation/emulation architecture for functional verification, Proceedings of the 38th conference on Design automation, p.623-628, June 2001, Las Vegas, Nevada, United States [doi>10.1145/378239.379036]
• 11: "PCI Local Bus Specification, Revision 2.1" PCISig, 1995.
• 12: Zebu, "http://www.eve-team.com"
• 13: Alpha data "http://www.alpha-data.com/"
• 14: PLX, "http://www.plxtech.com"
• 15: Xilinx, "http://www.xilinx.com"
• 16: Xilinx, Application Note, APP151 "http://www.xilinx.com/bvdocs/appnotes/xapp151.pdf"

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids

General Terms:
Design, Experimentation, Verification

Keywords:
C/C++ simulator, FPGA emulation, co-verification