| DyAD: smart routing for networks-on-chip |
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Annual ACM IEEE Design Automation Conference
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Proceedings of the 41st annual Design Automation Conference
table of contents
San Diego, CA, USA
SESSION: Memory and network optimization in embedded designs
table of contents
Pages: 260 - 263
Year of Publication: 2004
ISBN:1-58113-828-8
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Downloads (6 Weeks): 21, Downloads (12 Months): 130, Citation Count: 40
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ABSTRACT
In this paper, we present and evaluate a novel routing scheme called DyAD which combines the advantages of both deterministic and adaptive routing schemes. More precisely, we envision a new routing technique which judiciously switches between deterministic and adaptive routing based on the network's congestion conditions. The simulation results show the effectiveness of DyAD by comparing it with purely deterministic and adaptive routing schemes under different traffic patterns. Moreover, a prototype router based on the DyAD idea has been designed and evaluated. Compared to purely adaptive routers, the overhead of implementing DyAD is negligible (less than 7%), while the performance is consistently better.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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J. Hu and R. Marculescu. Smart routing for networks-on-chip. Technical report, ECE Department, Carnegie Mellon University, March 2004. Available at http://www.ece.cmu.edu/.sld/pubs.
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E. Rijpkema , K. G. W. Goossens , A. Radulescu , J. Dielissen , J. van Meerbergen , P. Wielage , E. Waterlander, Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip, Proceedings of the conference on Design, Automation and Test in Europe, p.10350, March 03-07, 2003
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CITED BY 40
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Leonel Tedesco , Aline Mello , Diego Garibotti , Ney Calazans , Fernando Moraes, Traffic generation and performance evaluation for mesh-based NoCs, Proceedings of the 18th annual symposium on Integrated circuits and system design, September 04-07, 2005, Florianolpolis, Brazil
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Jongman Kim , Dongkook Park , T. Theocharides , N. Vijaykrishnan , Chita R. Das, A low latency router supporting adaptivity for on-chip interconnects, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
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Krishna Sekar , Kanishka Lahiri , Anand Raghunathan , Sujit Dey, FLEXBUS: a high-performance system-on-chip communication architecture with a dynamically configurable topology, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
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Giuseppe Ascia , Vincenzo Catania , Maurizio Palesi , Davide Patti, A new selection policy for adaptive routing in network on chip, Proceedings of the 5th WSEAS International Conference on Electronics, Hardware, Wireless and Optical Communications, p.94-99, February 15-17, 2006, Madrid, Spain
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Erno Salminen , Tero Kangas , Timo D. Hämäläinen , Jouni Riihimäki , Vesa Lahtinen , Kimmo Kuusilinna, HIBI Communication Network for System-on-Chip, Journal of VLSI Signal Processing Systems, v.43 n.2-3, p.185-205, June 2006
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Srinivasan Murali , David Atienz , Luca Benini , Giovanni De Michel, A multi-path routing strategy with guaranteed in-order packet delivery and fault-tolerance for networks on chip, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
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J. W. van den Brand , C. Ciordas , K. Goossens , T. Basten, Congestion-controlled best-effort communication for networks-on-chip, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
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Evgeny Bolotin , Israel Cidon , Ran Ginosar , Avinoam Kolodny, Routing table minimization for irregular mesh NoCs, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
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Pejman Lotfi-Kamran , Masoud Daneshtalab , Caro Lucas , Zainalabedin Navabi, BARP-a dynamic routing protocol for balanced distribution of traffic in NoCs, Proceedings of the conference on Design, automation and test in Europe, March 10-14, 2008, Munich, Germany
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Avinash Karanth Kodi , Ashwini Sarathy , Ahmed Louri , Janet Wang, Adaptive inter-router links for low-power, area-efficient and reliable Network-on-Chip (NoC) architectures, Proceedings of the 2009 Conference on Asia and South Pacific Design Automation, January 19-22, 2009, Yokohama, Japan
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Maurizio Palesi , Giuseppe Longo , Salvatore Signorino , Rickard Holsmark , Shashi Kumar , Vincenzo Catania, Design of Bandwidth Aware and Congestion Avoiding Efficient Routing Algorithms for Networks-on-Chip Platforms, Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip, p.97-106, April 07-10, 2008
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