An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive distributed memory

ABSTRACT

Massive data transfer encountered in emerging multimedia embedded applications requires architecture allowing both highly distributed memory structure and multiprocessor computation to be handled. The key issue that needs to be solved is then how to manage data transfers between large numbers of distributed memories. To overcome this issue, our paper proposes a scalable Distributed Memory Server (DMS) for multiprocessor SoC (MPSoC). The proposed DMS is composed of: (1) high-performance and flexible memory service access points (MSAPs), which execute data transfers without intervention of the processing elements, (2) data network, and (3) control network. It can handle direct massive data transfer between the distributed memories of an MPSoC. The scalability and flexibility of the proposed DMS are illustrated through the implementation of an MPEG4 video encoder for QCIF and CIF formats. The experiments show clearly how DMS can be adapted to accommodate different SoC configurations requiring various data transfer bandwidths. Synthesis results show that bandwidth can scale up to 28.8 GB/sec.

REFERENCES

• 1: K. Keutzer et al. "System-level design: Orthogonalization of concerns and platform-based design," IEEE Trans. On CAD of Integrated Circuits and Systems.
• 2: David E. Culler , Anoop Gupta , Jaswinder Pal Singh, Parallel Computer Architecture: A Hardware/Software Approach, Morgan Kaufmann Publishers Inc., San Francisco, CA, 1997
• 3: A. Baghdadi , D. Lyonnard , N. Zergainoh , A. Jerraya, An efficient architecture model for systematic design of application-specific multiprocessor SoC, Proceedings of the conference on Design, automation and test in Europe, p.55-63, March 2001, Munich, Germany
• 4: Jerraya et al., "Component-Based Design Approach for Multicore SoCs," in Proceedings of DAC'02.
• 5: ARM PrimeCell™ DMA Controller, http://www.arm.com/armtech/PrimeCell?OpenDocument.
• 6: Dave Comisky , Charles Fuoco, A Scalable High-Performance DMA Architecture for DSP Applications, Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors, p.414, September 17-20, 2000
• 7: MemMax™ Memory Scheduler, http://www.sonicsinc.com/sonics/products/memmax
• 8: Andrei Rdulescu , John Dielissen , Kees Goossens , Edwin Rijpkema , Paul Wielage, An Efficient On-Chip Network Interface Offering Guaranteed Services, Shared-Memory Abstraction, and Flexible Network Configuration, Proceedings of the conference on Design, automation and test in Europe, p.20878, February 16-20, 2004
• 9: Praveen Bhojwani , Rabi Mahapatra, Interfacing Cores with On-chip Packet-Switched Networks, Proceedings of the 16th International Conference on VLSI Design, p.382, January 04-08, 2003
• 10: E. Rijpkema , K. G. W. Goossens , A. Radulescu , J. Dielissen , J. van Meerbergen , P. Wielage , E. Waterlander, Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip, Proceedings of the conference on Design, Automation and Test in Europe, p.10350, March 03-07, 2003
• 11: William J. Dally and Brian Towles,"Route Packets, Not Wires: On-Chip Interconnection Networks," in Proceedings of DAC'02.
• 12: Philips Nexperia™ DVP, http://www.semiconductors.philips.com/platforms/nexperia
• 13: TI OMAP™ Platform, http://www.ti.com/sc/docs/apps/omap/overview.htm
• 14: MPEG-4 Standard, http://www.chiariglione.org/mpeg/standards/mpeg-4/mpeg-4.htm
• 15: Motorola DSP56311, http://www.motorola.com/brdata/PDFDB/docs/DSP56311.pdf
• 16: ARM ARM946E-S, http://www.arm.com/products/CPUs/ARM946ES.html
• 17: T. P. McMahon , A. Skjellum, eMPI/eMPICH: Embedding MPI, Proceedings of the Second MPI Developers Conference, p.180, July 01-02, 1996
• 18: James Kohout , Alan D. George, A high-performance communication service for parallel computing on distributed DSP systems, Parallel Computing, v.29 n.7, p.851-878, July 2003 [doi>10.1016/S0167-8191(03)00061-9]
• 19: Junyu Peng , Daniel Gajski, Optimal message-passing for data coherency in distributed architecture, Proceedings of the 15th international symposium on System Synthesis, October 02-04, 2002, Kyoto, Japan [doi>10.1145/581199.581206]

INDEX TERMS

Primary Classification:
  B. Hardware
  B.4 INPUT/OUTPUT AND DATA COMMUNICATIONS
      B.4.3 Interconnections (subsystems)

Additional Classification:
  B. Hardware
  B.8 Performance and Reliability

General Terms:
Design, Experimentation, Performance

Keywords:
data transfer architecture, memory server, message passing, multiprocessor SoC, network interface, network on chip