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An efficient finite-domain constraint solver for circuits
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 41st annual Design Automation Conference table of contents
San Diego, CA, USA
SESSION: Abstraction techniques for functional verification table of contents
Pages: 212 - 217  
Year of Publication: 2004
ISBN:1-58113-828-8
Authors
G. Parthasarathy  University of California, Santa Barbara, CA
M. K. Iyer  University of California, Santa Barbara, CA
K.-T. Cheng  University of California, Santa Barbara, CA
L.-C. Wang  University of California, Santa Barbara, CA
Sponsors
ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 8,   Downloads (12 Months): 20,   Citation Count: 6
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ABSTRACT

We present a novel hybrid finite-domain constraint solving engine for RTL circuits, that automatically uses data-path abstraction. We describe how DPLL search can be modified by using efficient finite-domain constraint propagation to improve communication between interacting integer and Boolean domains. This enables efficient combination of Boolean SAT and linear integer arithmetic solving techniques. We use conflict-based learning using the variables on the boundary of control and data-path for additional performance benefits. Finally, the hybrid constraint solver is experimentally analyzed using some example circuits.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Collaborative Colleagues:
G. Parthasarathy: colleagues
M. K. Iyer: colleagues
K.-T. Cheng: colleagues
L.-C. Wang: colleagues