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Routing architecture exploration for regular fabrics
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 41st annual Design Automation Conference table of contents
San Diego, CA, USA
SESSION: Methods for a priori feasible layout generation table of contents
Pages: 204 - 207  
Year of Publication: 2004
ISBN:1-58113-828-8
Authors
V. Kheterpal  Carnegie Mellon University, Pittsburgh, PA
A. J. Strojwas  Carnegie Mellon University, Pittsburgh, PA
L. Pileggi  Carnegie Mellon University, Pittsburgh, PA
Sponsors
ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 6,   Downloads (12 Months): 28,   Citation Count: 6
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ABSTRACT

In an effort to control the parameter variations and systematic yield problems that threaten the affordability of application-specific ICs, new forms of design regularity and structure have been proposed. For example, there has been speculation [6] that regular logic fabrics [1] based on regular geometry patterns [2] can offer tighter control of variations and greater control of systematic manufacturing failures. In this paper we describe a routing framework that accommodates arbitrary descriptions of regular and structured routing architectures. We further propose new regular routing architectures and explore the various performance vs. manufacturability trade-offs. Results demonstrate that a more regular, restricted routing architecture can provide a substantial advantage in terms of manufacturability and predictability while incurring a moderate performance penalty.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

1
 
2
M. Palusinski, A. J. Strojwas and W. Maly, "Regularity in Physical Design", GSRC Workshop, Las Vages, June 2001.
 
3
A. J. Strojwas, "Process-Design Interaction Modeling Based Design For Manufacturability", Tutorial, DAC-2003.
 
4
 
5
D.T. Blaauw et al, "Statistical Timing Analysis using Bounds and Selective Enumeration", IEEE Trans. on CAD of Integrated Circuits and Systems, Vol. 22, No.9, Sep 2003.
 
6
B. Tyrrell et al, "Investigation of the physical and practical limits of dense-only phase shift lithography for circuit feature definition", Society of Photo-Optical Instrumentation Engineers, October-2002.
 
7
Gonzales, Anthony J. et al, "Recent results in the application of e-beam direct-write lithography", Proc. SPIE Vol. 1089, p. 37.


Collaborative Colleagues:
V. Kheterpal: colleagues
A. J. Strojwas: colleagues
L. Pileggi: colleagues