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Profile-based optimal intra-task voltage scheduling for hard real-time applications
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 41st annual Design Automation Conference table of contents
San Diego, CA, USA
SESSION: Power modeling and optimization for embedded systems table of contents
Pages: 87 - 92  
Year of Publication: 2004
ISBN:1-58113-828-8
Authors
Jaewon Seo  CS, KAIST
Taewhan Kim  EE, Seoul National University
Ki-Seok Chung  CIC, Hanyang University
Sponsors
ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 5,   Downloads (12 Months): 22,   Citation Count: 10
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ABSTRACT

This paper presents a set of comprehensive techniques for the intra-task voltage scheduling problem to reduce energy consumption in hard real-time tasks of embedded systems. Based on the execution profile of the task, a voltage scheduling technique that optimally determines the operating voltages to individual basic blocks in the task is proposed. The obtained voltage schedule guarantees minimum average energy consumption. (The proof of the optimality is included.) The proposed technique is then extended to solve practical issues regarding transition overheads, which are totally or partially ignored in the existing approaches. Finally, a technique involving a novel extension of our optimal scheduler is proposed to solve the scheduling problem in a discretely variable voltage environment. In summary, it is confirmed from experiments that the proposed optimal scheduling technique reduces energy consumption by 20.2 over that of one of the state-of-the-art schedulers citeshin2 and, further, the extended technique in a discrete voltage environment reduces energy consumption by 45.3 on average.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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D. Mosse it et al., "Compiler-Assisted Dynamic Power-Aware Scheduling for Real-Time Applications", COLP, 2000.
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Intel Corporation, Enhanced Intel SpeedStep technology, 2003 http://www.intel.com
 
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Advanced Micro Devices, Inc. AMD PowerNow! technology, 2003 http://www.amd.com
 
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Transmeta Corporation, Crusoe Processor Specification, 2003 http://www.transmeta.com
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W. H. Press, B. P. Flannery, S. A. Teukolsky and W. T. Vetterling, Numerical Recipes in C, Cambridge University Press, 1988.

CITED BY  10

Collaborative Colleagues:
Jaewon Seo: colleagues
Taewhan Kim: colleagues
Ki-Seok Chung: colleagues