Design and reliability challenges in nanometer technologies

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Design and reliability challenges in nanometer technologies

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 41st annual Design Automation Conference table of contents

San Diego, CA, USA

SESSION: Reliable system-on-a-chip design in the nanometer era table of contents

Pages: 75 - 75

Year of Publication: 2004

ISBN:1-58113-828-8

Authors

Shekhar Borkar	Intel Labs, Hillsboro, OR
Tanay Karnik	Intel Labs, Hillsboro, OR
Vivek De	Intel Labs, Hillsboro, OR

Sponsors

ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 26, Downloads (12 Months): 136, Citation Count: 21

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abstract references cited by index terms collaborative colleagues

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ABSTRACT

CMOS technology scaling is causing the channel lengths to be sub-wavelength of light. Parameter variation, caused by sub-wavelength lithography, will pose a major challenge for design and reliability of future high performance microprocessors in nanometer technologies. In this paper, we present the impact of these variations on processor functionality, predictability and reliability. We propose design and CAD solutions for variation tolerance. We conclude this paper with soft error rate scaling trends and soft error tolerant circuits for reliability enhancement.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Tanay Karnik , Shekhar Borkar , Vivek De, Sub-90nm technologies: challenges and opportunities for CAD, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.203-206, November 10-14, 2002, San Jose, California [doi>10.1145/774572.774602]
	2	Shekhar Borkar , Tanay Karnik , Siva Narendra , Jim Tschanz , Ali Keshavarzi , Vivek De, Parameter variations and impact on circuits and microarchitecture, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA [doi>10.1145/775832.775920]

CITED BY 21

	Vineet Wason , Kaustav Banerjee, A probabilistic framework for power-optimal repeater insertion in global interconnects under parameter variations, Proceedings of the 2005 international symposium on Low power electronics and design, August 08-10, 2005, San Diego, CA, USA
	Jim Tschanz , Keith Bowman , Vivek De, Variation-tolerant circuits: circuit solutions and techniques, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Diana Marculescu , Emil Talpes, Variability and energy awareness: a microarchitecture-level perspective, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	A. Papanikolaou , F. Lobmaier , H. Wang , M. Miranda , F. Catthoor, A system-level methodology for fully compensating process variability impact of memory organizations in periodic applications, Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, September 19-21, 2005, Jersey City, NJ, USA
	Peter Zipf, Applying dynamic reconfiguration for fault tolerance in fine-grained logic arrays, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.16 n.2, p.134-143, February 2008
	Alan L. Cox , Kartik Mohanram , Scott Rixner, Dependable ≠ unaffordable, Proceedings of the 1st workshop on Architectural and system support for improving software dependability, p.58-62, October 21-21, 2006, San Jose, California
	Kypros Constantinides , Stephen Plaza , Jason Blome , Valeria Bertacco , Scott Mahlke , Todd Austin , Bin Zhang , Michael Orshansky, Architecting a reliable CMP switch architecture, ACM Transactions on Architecture and Code Optimization (TACO), v.4 n.1, p.2-es, March 2007
	Swaroop Ghosh , Swarup Bhunia , Kaushik Roy, A new paradigm for low-power, variation-tolerant circuit synthesis using critical path isolation, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California
	Nam Sung Kim , Taeho Kgil , K. Bowman , V. De , T. Mudge, Total power-optimal pipelining and parallel processing under process variations in nanometer technology, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.535-540, November 06-10, 2005, San Jose, CA
	C. Sanz , M. Prieto , A. Papanikolaou , M. Miranda , F. Catthoor, System-level process variability compensation on memory organizations of dynamic applications: a case study, Proceedings of the 7th International Symposium on Quality Electronic Design, p.376-382, March 27-29, 2006
	Diana Marculescu , Emil Talpes, Energy Awareness and Uncertainty in Microarchitecture-Level Design, IEEE Micro, v.25 n.5, p.64-76, September 2005
	Concepción Sanz , Manuel Prieto , José Ignacio Gómez , Antonis Papanikolaou , Miguel Miranda , Francky Catthoor, Combining system scenarios and configurable memories to tolerate unpredictability, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.13 n.3, p.1-7, July 2008
	Philip M. Wells , Koushik Chakraborty , Gurindar S. Sohi, Adapting to intermittent faults in multicore systems, ACM SIGPLAN Notices, v.43 n.3, March 2008
	Hamed F. Dadgour , Kaustav Banerjee, Design and analysis of hybrid NEMS-CMOS circuits for ultra low-power applications, Proceedings of the 44th annual conference on Design automation, June 04-08, 2007, San Diego, California
	Debabrata Mohapatra , Georgios Karakonstantis , Kaushik Roy, Low-power process-variation tolerant arithmetic units using input-based elastic clocking, Proceedings of the 2007 international symposium on Low power electronics and design, August 27-29, 2007, Portland, OR, USA
	Bonesi Stefano , Davide Bertozzi , Luca Benini , Enrico Macii, Process variation tolerant pipeline design through a placement-aware multiple voltage island design style, Proceedings of the conference on Design, automation and test in Europe, March 10-14, 2008, Munich, Germany
	Medardoni Simone , Marcello Lajolo , Davide Bertozzi, Variation tolerant NoC design by means of self-calibrating links, Proceedings of the conference on Design, automation and test in Europe, March 10-14, 2008, Munich, Germany
	Concepción Sanz , Manuel Prieto , José Ignacio Gómez , Antonis Papanikolaou , Francky Catthoor, System-level process variability compensation on memory organizations: on the scalability of multi-mode memories, Proceedings of the 2009 Conference on Asia and South Pacific Design Automation, January 19-22, 2009, Yokohama, Japan
	Girish Vishnu Varatkar , Naresh R. Shanbhag, Error-resilient motion estimation architecture, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.16 n.10, p.1399-1412, October 2008
	Ruijing Shen , Ning Mi , Sheldon X.-D. Tan , Yici Cai , Xianlong Hong, Statistical modeling and analysis of chip-level leakage power by spectral stochastic method, Proceedings of the 2009 Conference on Asia and South Pacific Design Automation, January 19-22, 2009, Yokohama, Japan
	Sudeep Pasricha , Young-Hwan Park , Nikil Dutt , Fadi J. Kurdahi, System-level PVT variation-aware power exploration of on-chip communication architectures, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.14 n.2, p.1-25, March 2009