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Modular scheduling of guarded atomic actions
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 41st annual Design Automation Conference table of contents
San Diego, CA, USA
SESSION: Timing -- driven system synthesis table of contents
Pages: 55 - 60  
Year of Publication: 2004
ISBN:1-58113-828-8
Authors
Daniel L. Rosenband  Massachusetts Institute of Technology, Cambridge, MA
Arvind  Massachusetts Institute of Technology, Cambridge, MA
Sponsors
ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 8,   Downloads (12 Months): 28,   Citation Count: 5
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ABSTRACT

A modular synthesis flow is essential for a scalable and hierarchical design methodology. This paper considers a particular modular flow where each module has interface methods and the internal behavior of the module is described in terms of a set of guarded atomic actions on the state elements of the module. A module can also read and update the state of other modules but only by invoking the interface methods of those modules. This paper extends the past work on hardware synthesis of a set of guarded atomic actions by Hoe and Arvind to modules of such actions. It presents an algorithm that, given the scheduling constraints on the interface methods of the called modules, derives the "glue logic" and the scheduling constraints for the interface methods of the calling module such that the atomicity of the guarded actions is preserved across module boundaries. Such modules provide reusable IP which facilitates "correctness by construction" design methodology. It also reduces compile-times dramatically in comparison to the compilation that flattens all the modules first.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Edwards, S.A., High-level Synthesis from the Synchronous Language Esterel. in Proceedings of the International Workshop of Logic and Synthesis (IWLS), (New Orleans, Louisiana, 2002).
 
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Hoe, J.C. Operation-centric hardware description and synthesis Dept. of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, 2000, 139 p.
 
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Collaborative Colleagues:
Daniel L. Rosenband: colleagues
Arvind: colleagues