Simulation of ram-based asynchronous sequential circuits

ABSTRACT

We have developed a computer simulator for the asynchronous sequential circuits (ASCs) constructed by using the random access memories (RAMs). This is a generic simulator with respect to the manufacturing technology of the RAM because all the time delays are variables and can be changed by the user. In addition, there is no restriction on the RAM size. The simulated RAM can be programmed and then the simulator simulates the ASC with its direct feedback connections. The durations of the transition states are generated in a random fashion. The user can change the input state interactively from the keyboard and the output state of the ASC is continuously displayed on the monitor screen.

REFERENCES

• 1: Ditzinger, A. and H.M. Lipp. 1975. "Use of Hemorles and Programmable Logic Arrays for Asynchronous Sequential Circuits." Computer and Digital Techniques, Vol. 2: 213-220.
• 2: Pradhan, D.K. 1978. "Fault-Tolerant Asynchronous Networks using Read-Only Memories," IEEE Transactions on Computers, Vol. C-27: 674-679~
• 3: $ho11, H.A. and S.C. Yang. 1975. "Design of Asynchronous Sequentlal Networks using Read-Only Memorles." IEEE TRANSACTIONS on COMPUTERS, Vol. c-24: 195-206.
• 4: Thomas, B. and P.C. Chandrasekharan. 1981. "Economical Realization of Asynchronous Sequential Circuits using Random Access Memories." IEE Proceedings, Vol. 128: 129-132.
• 5: Stephen H. Unger, Asynchronous Sequential Switching Circuit, Krieger Publishing Co., Inc., Melbourne, FL, 1983

INDEX TERMS

Primary Classification:
  F. Theory of Computation
  F.1 COMPUTATION BY ABSTRACT DEVICES

Additional Classification:
  B. Hardware
  B.3 MEMORY STRUCTURES
  B.4 INPUT/OUTPUT AND DATA COMMUNICATIONS
      B.4.3 Interconnections (subsystems)
          Subjects: Asynchronous/synchronous operation
      B.4.4 Performance Analysis and Design Aids**
          Subjects: Simulation**

General Terms:
Design