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On Compacting Test Response Data Containing Unknown Values
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Source International Conference on Computer Aided Design archive
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design table of contents
Page: 855  
Year of Publication: 2003
ISBN ~ ISSN:1092-3152 , 1-58113-762-1
Authors
Chen Wang  Mentor Graphic Corporation, Wilsonville, OR
Sudhakar M. Reddy  University of Iowa, Iowa City
Irith Pomeranz  Purdue University, West Lafayette, IN
Janusz Rajski  Mentor Graphic Corporation, Wilsonville, OR
Jerzy Tyszer  Poznan University of Technology, Poland
Sponsor
SIGDA: ACM Special Interest Group on Design Automation
Publisher
IEEE Computer Society  Washington, DC, USA
Bibliometrics
Downloads (6 Weeks): 5,   Downloads (12 Months): 22,   Citation Count: 8
Additional Information:

abstract   references   cited by   index terms   collaborative colleagues  

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DOI Bookmark: 10.1109/ICCAD.2003.105

ABSTRACT

The design of a test response compactor called a Block Compactoris given. Block Compactors belong to a new class of compactorscalled Finite Memory Compactors. Different from spacecompactors, finite memory compactors contain memory elements.Also unlike time compactors, finite memory compactors havefinite impulse response. These properties give finite memorycompactors the ability to achieve higher compaction ratios thanspace compactors and still be able to tolerate unknown values intest responses. The proposed Block Compactors, as an instance offinite memory compactors generate a signature of response data inseveral scan cycles. Results presented on several industrial designsshow that Block Compactors provide better test quality and higherdata compaction than earlier works on test response compactors.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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[1] Pomeranz, L. N. Reddy and S. M. Reddy, "COMPACTEST: A Method to Generate Compact test Sets for Combinational Circuits," IEEE Trans. CAD, pp. 1040-1049, 1993.
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[3] M. Abramovici, M.A. Breuer and A.D. Friedman, "Digital Systems Testing and Testable Design", IEEE Press.
 
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[4] B. Koneman, "LFSR-Coded Test Patterns for Scan Designs," Proc. European Test Conf, pp. 237-242, 1993.
 
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[12] K.K. Saluja and M. Karpovsky, "Testing computer hardware through data compression in space and time," Proc. ITC, pp. 83-88, 1983.
 
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[18] J. Rajski, J. Tyszer, C. Wang and S.M. Reddy, "Convolutional Compaction of Test Responses," Proc. of ITC, 2003.

CITED BY  8

Collaborative Colleagues:
Chen Wang: colleagues
Sudhakar M. Reddy: colleagues
Irith Pomeranz: colleagues
Janusz Rajski: colleagues
Jerzy Tyszer: colleagues