Switch-Factor Based Loop RLC Modeling for Efficient Timing Analysis

ABSTRACT

Timing uncertainty caused by inductive and capacitivecoupling is one of the major bottlenecks in timing analysis. In thispaper, we propose an effective loop RLC modeling technique toefficiently decouple lines with both inductive and capacitivecoupling. We generalize the RLC decoupling problem based ontransmission line theory and a switch-factor, which is the voltageratio between two nets. This switch-factor is also known as theMiller factor and is widely used to model capacitive coupling.The proposed modeling technique can be directly applied to partialRLC netlists extracted using existing parasitic extraction toolswithout advance knowledge of the return path. The new modelaccurately captures the impact of neighboring switching activitywhen it significantly affects the size of current return loop. Asdemonstrated in our experiments, the new model accuratelypredicts both upper and lower delay bounds as a function ofneighboring switching patterns. Therefore, this approach can beeasily implemented into existing timing analysis flows such asmax-timing and min-timing analysis. Finally, we apply the newmodeling approach to a range of activities across the designprocess including timing optimization, static timing analysis, highfrequency clock design, and data-bus wire planning.

REFERENCES

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION
      B.5.1 Design
          Subjects: Data-path design

Additional Classification:
  B. Hardware
  B.4 INPUT/OUTPUT AND DATA COMMUNICATIONS
      B.4.3 Interconnections (subsystems)
          Subjects: Asynchronous/synchronous operation
  B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION
      B.5.2 Design Aids
          Subjects: Simulation

General Terms:
Algorithms, Design, Performance

Keywords:
RLC model, loop inductance, switch-factor, current return loop, static timing analysis, slew rate, data-bus, and clock