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ABSTRACT
We propose a new circuit analysis method, namelySemi-Implicit Linear-Centric Analysis (SILCA), for efficientSPICE-accurate transient simulation of deep-submicron VLSIcircuits with strong parasitic coupling effects introduced byinterconnect lines, common substrate, power/ground networks, etc.SILCA is based on two linear-centric techniques. First, a new semi-implicititerative numerical integration scheme is developed, whichapplies dynamic time step control accounting for stiff systems andmeanwhile keeps constant equivalent conductance forcapacitor/inductor companion models. Its convergence and stabilityproperties are characterized. Second, to achieve constant linearizedconductance for nonlinear devices during nonlinear iterationprocess, a successive variable chord method is introduced as analternative of the Newton-Raphson method and the rank-one updatetechnique is implemented for fast LU factorization. With thesetechniques, SILCA reduces the number and cost of required LUfactorizations dramatically. Experimental results on substrate andpower/ground networks have demonstrated that SILCA yieldsSPICE-like accuracy with an over 80X reduction in LUfactorization cost, and an about 20X overall CPU time speedup overSPICE3 for circuits with tens of thousands elements, and theefficiency increases further with the size of a circuit.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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1
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2
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[2] A. Samavedam, A. Sadate, K. Mayaram, and T. S. Fiez, "A Scalable Substrate Noise Coupling Model for Design of Mixed-Signal IC's", IEEE Journal of Solid-State Circuits, vol. 35, no. 6, pp. 895-904, June 2000.
|
| |
3
|
[3] M. Nagata, J. Nagai, K. Hijikata, T. Morie, and A. Iwata, "Physical Design Guides for Substrate Noise Reduction in CMOS Digital Circuits", IEEE Journal of Solid-State Circuits, vol. 36, No. 3, pp. 539-549, March 2001.
|
| |
4
|
|
| |
5
|
[5] L. W. Nagel, SPICE: A Computer Program to Simulate Semiconductor Circuits, University of California, Berkeley, Tech. Rep., UCB/ERL M520, May 1975.
|
| |
6
|
|
| |
7
|
|
| |
8
|
[8] K. S. Kundert and A. Sangiovanni-Vincentelli, Sparse User's Guide - A Sparse Linear Equation Solver Version 1.3a, University of California, Berkeley, April 1988.
|
| |
9
|
[9] E. Acar, F. Dartu, and L. T. Pileggi, "TETA: Transistor-Level Waveform Evaluation for Timing Analysis", IEEE Trans. on Computer-Aided Design, vol. 21, no. 5, pp. 605-616, May 2002.
|
| |
10
|
[10] A. Odabasioglu, M. Celik, and L. T. Pillegi, "PRIMA: Passive Reduced-Order Interconnect Macromodeling Algorithm", IEEE Trans. on Computer-Aided Design, vol. 17, no. 8, pp. 645-654, August 1998.
|
| |
11
|
|
| |
12
|
[12] T. Fujisawa, E. S. Kuh, and T. Ohtsuki, "A Sparse Matrix Method for Analysis of Piecewise-Linear Resistive Networks", IEEE Trans. on Circuit Theory, vol. CT-19, no. 6, pp. 571-584, November 1972.
|
| |
13
|
[13] J. T. J. van Eijndhoven and M. T. van Stiphout, "Latency Exploitation in Circuit Simulation by Sparse Matrix Techniques", Proc. IEEE int. Symp. on Circuits and Systems, pp. 623-626, June 1988.
|
| |
14
|
|
 |
15
|
|
| |
16
|
[16] Y. Wang, V. Jandhyala, and C.-J. R. Shi, "Coupled Electromagnetic-Circuit Simulation of Arbitrarily-Shaped Conducting Structures", Proc. IEEE Conf. On Electrical Performance of Electronic Packaging, pp. 233-236, October 2001.
|
| |
17
|
[17] L. R. Petzold, "A Description of DASSL: A Differential/Algebraic System Solver", IMACS Trans. Scientific Computing, R. Stepleman et al. (eds.), vol. 1, pp. 65-68, 1983.
|
| |
18
|
[18] P. F. Cox, R. G. Burch, P. Yang, and D. E. Hocevar, "New Implicit Integration Method for Efficient Latency Exploration in Circuit Simulation", IEEE Trans. on Computer-Aided Design, vol. 8, no. 10, pp. 1051-1064, October 1989.
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CITED BY 6
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Zhengyong Zhu , Khosro Rouz , Manjit Borah , Chung-Kuan Cheng , Ernest S. Kuh, Efficient transient simulation for transistor-level analysis, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
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