Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal

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Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal

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International Conference on Computer Aided Design archive
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design table of contents

Page: 621

Year of Publication: 2003

ISBN ~ ISSN:1092-3152 , 1-58113-762-1

Authors

Hongliang Chang	University of Minnesota
Sachin S. Sapatnekar	University of Minnesota

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

IEEE Computer Society Washington, DC, USA

Bibliometrics

Downloads (6 Weeks): 13, Downloads (12 Months): 131, Citation Count: 140

Additional Information:

abstract references cited by index terms collaborative colleagues

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DOI Bookmark:	10.1109/ICCAD.2003.129

ABSTRACT

We present an efficient statistical timing analysis algorithm thatpredicts the probability distribution of the circuit delay while incorporatingthe effects of spatial correlations of intra-die parametervariations, using a method based on principal component analysis.The method uses a PERT-like circuit graph traversal, and hasa run-time that is linear in the number of gates and interconnects,as well as the number of grid partitions used to model spatial correlations.On average, the mean and standard deviation valuescomputed by our method have errors of 0.2% and 0.9%, respectively,in comparison with a Monte Carlo simulation.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	[1] M. Berkelaar, "Statistical Delay Calculation, a Linear Time Method," in Proc. TAU, pp. 15-24, 1997.
	2	Aseem Agarwal , David Blaauw , Vladimir Zolotov , Sarma Vrudhula, Statistical timing analysis using bounds and selective enumeration, Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems, December 02-03, 2002, Monterey, California, USA [doi>10.1145/589411.589417]
	3	Jing-Jia Liou , Kwang-Ting Cheng , Sandip Kundu , Angela Krstic, Fast statistical timing analysis by probabilistic event propagation, Proceedings of the 38th conference on Design automation, p.661-666, June 2001, Las Vegas, Nevada, United States [doi>10.1145/378239.379043]
	4	Srinath R. Naidu, Timing Yield Calculation Using an Impulse-train Approach, Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design, p.219, January 07-11, 2002
	5	[5] S. Tsukiyama, M. Tanaka, and M. Fukui, "A New Statistical Static Timing Analyzer Considering Correlation Between Delays," in Proc. TAU, pp. 27-33, Dec 2000.
	6	Jing-Jia Liou , Angela Krstic , Li-C. Wang , Kwang-Ting Cheng, False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA [doi>10.1145/513918.514061]
	7	Michael Orshansky , Kurt Keutzer, A general probabilistic framework for worst case timing analysis, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA [doi>10.1145/513918.514059]
	8	Byungwoo Choi , D. M. H. Walker, Timing Analysis of Combinational Circuits Including Capacitive Coupling and Statistical Process Variation, Proceedings of the 18th IEEE VLSI Test Symposium (VTS'00), p.49, April 30-May 04, 2000
	9	[9] A. Agarwal, D. Blaauw, S. Sundareswaran, V. Zolotov, M. Zhou, K. Gala, and R. Panda, "Path-Based Statistical Timing Analysis Considering Inter- and Intra-die Correlations," in Proc. TAU, pp. 16-21, 2002.
	10	Ying Liu , Sani R. Nassif , Lawrence T. Pileggi , Andrzej J. Strojwas, Impact of interconnect variations on the clock skew of a gigahertz microprocessor, Proceedings of the 37th conference on Design automation, p.168-171, June 05-09, 2000, Los Angeles, California, United States [doi>10.1145/337292.337365]
	11	[11] D. F. Morrison, "Multivariate Statistical Methods," New York: McGraw-Hill, 1976.
	12	[12] C. E. Clark, "The Greatest of a Finite Set of Random Variables," Operations Research, vol. 9, pp. 85-91, 1961.
	13	[13] J. Cong, "Challenges and Opportunities for Design Innovations in Nanometer Technologies," SRC Design Science Concept Paper, 1997.
	14	[14] S. Nassif, "Delay Variability: Sources, Impact and Trends," in Proc. ISSCC, pp. 368-369, 2000
	15	[15] A. Caldwell, A. B. Kahng, and I. Markov, "Capo: a large-scale fixed-die placer," avail. at http://vlsicad.ucsd.edu/GSRC/bookshelf/Slots/Placement.

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	Jaskirat Singh , Vidyasagar Nookala , Zhi-Quan Luo , Sachin Sapatnekar, Robust gate sizing by geometric programming, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
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	Khaled R. Heloue , Farid N. Najm, Parameterized timing analysis with general delay models and arbitrary variation sources, Proceedings of the 45th annual conference on Design automation, June 08-13, 2008, Anaheim, California
	Xiaoji Ye , Yaping Zhan , Peng Li, Statistical leakage power minimization using fast equi-slack shell based optimization, Proceedings of the 44th annual conference on Design automation, June 04-08, 2007, San Diego, California
	Jongyoon Jung , Taewhan Kim, Timing variation-aware high-level synthesis, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
	Ying-Yen Chen , Jing-Jia Liou, Extraction of statistical timing profiles using test data, Proceedings of the 44th annual conference on Design automation, June 04-08, 2007, San Diego, California
	Feng Wang , C. Nicopoulos , Xiaoxia Wu , Yuan Xie , N. Vijaykrishnan, Variation-aware task allocation and scheduling for MPSoC, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
	Frank Liu, An efficient method for statistical circuit simulation, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
	Zhuo Feng , Peng Li , Yaping Zhan, Fast second-order statistical static timing analysis using parameter dimension reduction, Proceedings of the 44th annual conference on Design automation, June 04-08, 2007, San Diego, California
	Soo-Kwan Eo , Sungjoo Yoo , Kyu-Myung Choi, An industrial perspective of power-aware reliable SoC design, Proceedings of the 2008 conference on Asia and South Pacific design automation, January 21-24, 2008, Seoul, Korea
	Ruiming Chen , Lizheng Zhang , Vladimir Zolotov , Chandu Visweswariah , Jinjun Xiong, Static timing: back to our roots, Proceedings of the 2008 conference on Asia and South Pacific design automation, January 21-24, 2008, Seoul, Korea
	Katsumi Homma , Izumi Nitta , Toshiyuki Shibuya, Non-Gaussian statistical timing models of die-to-die and within-die parameter variations for full chip analysis, Proceedings of the 2008 conference on Asia and South Pacific design automation, January 21-24, 2008, Seoul, Korea
	Ruiming Chen , Hai Zhou, Timing budgeting under arbitrary process variations, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
	Vishal Khandelwal , Ankur Srivastava, Monte-Carlo driven stochastic optimization framework for handling fabrication variability, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
	Ruiming Chen , Hai Zhou, Fast min-cost buffer insertion under process variations, Proceedings of the 44th annual conference on Design automation, June 04-08, 2007, San Diego, California
	Ruilin Wang , Cheng-Kok Koh, A frequency-domain technique for statistical timing analysis of clock meshes, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
	Vivek Joshi , David Blaauw , Dennis Sylvester, Soft-edge flip-flops for improved timing yield: design and optimization, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
	Lerong Cheng , Jinjun Xiong , Lei He, Non-linear statistical static timing analysis for non-Gaussian variation sources, Proceedings of the 44th annual conference on Design automation, June 04-08, 2007, San Diego, California
	Brendan Hargreaves , Henrik Hult , Sherief Reda, Within-die process variations: how accurately can they be statistically modeled?, Proceedings of the 2008 conference on Asia and South Pacific design automation, January 21-24, 2008, Seoul, Korea
	Takashi Sato , Hiroyuki Ueyama , Noriaki Nakayama , Kazuya Masu, Determination of optimal polynomial regression function to decompose on-die systematic and random variations, Proceedings of the 2008 conference on Asia and South Pacific design automation, January 21-24, 2008, Seoul, Korea
	Guo Yu , Wei Dong , Zhuo Feng , Peng Li, A framework for accounting for process model uncertainty in statistical static timing analysis, Proceedings of the 44th annual conference on Design automation, June 04-08, 2007, San Diego, California
	Bogdan F. Romanescu , Michael E. Bauer , Sule Ozev , Daniel J. Sorin, VariaSim: simulating circuits and systems in the presence of process variability, ACM SIGARCH Computer Architecture News, v.35 n.5, p.45-48, December 2007
	Jinjun Xiong , Vladimir Zolotov , Chandu Visweswariah , Peter A. Habitz, Optimal margin computation for at-speed test, Proceedings of the conference on Design, automation and test in Europe, March 10-14, 2008, Munich, Germany
	Bonesi Stefano , Davide Bertozzi , Luca Benini , Enrico Macii, Process variation tolerant pipeline design through a placement-aware multiple voltage island design style, Proceedings of the conference on Design, automation and test in Europe, March 10-14, 2008, Munich, Germany
	Animesh Datta , Swarup Bhunia , Jung Hwan Choi , Saibal Mukhopadhyay , Kaushik Roy, Profit aware circuit design under process variations considering speed binning, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.16 n.7, p.806-815, July 2008
	Jinjun Xiong , Vladimir Zolotov , Chandu Visweswariah, Incremental criticality and yield gradients, Proceedings of the conference on Design, automation and test in Europe, March 10-14, 2008, Munich, Germany
	Cheng Zhuo , David Blaauw , Dennis Sylvester, Variation-aware gate sizing and clustering for post-silicon optimized circuits, Proceeding of the thirteenth international symposium on Low power electronics and design, August 11-13, 2008, Bangalore, India
	Gregory Lucas , Scott Cromar , Deming Chen, FastYield: variation-aware, layout-driven simultaneous binding and module selection for performance yield optimization, Proceedings of the 2009 Conference on Asia and South Pacific Design Automation, January 19-22, 2009, Yokohama, Japan
	Xiaoji Ye , Frank Liu , Peng Li, Fast variational interconnect delay and slew computation using quadratic models, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.8, p.913-926, August 2007
	Vladimir Zolotov , Jinjun Xiong , Hanif Fatemi , Chandu Visweswariah, Statistical path selection for at-speed test, Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design, November 10-13, 2008, San Jose, California
	Jason Cong , Puneet Gupta , John Lee, On the futility of statistical power optimization, Proceedings of the 2009 Conference on Asia and South Pacific Design Automation, January 19-22, 2009, Yokohama, Japan
	Khaled R. Heloue , Sari Onaissi , Farid N. Najm, Efficient block-based parameterized timing analysis covering all potentially critical paths, Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design, November 10-13, 2008, San Jose, California
	Kaviraj Chopra , Cheng Zhuo , David Blaauw , Dennis Sylvester, A statistical approach for full-chip gate-oxide reliability analysis, Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design, November 10-13, 2008, San Jose, California
	HaNeul Chon , Taewhan Kim, Timing variation-aware task scheduling and binding for MPSoC, Proceedings of the 2009 Conference on Asia and South Pacific Design Automation, January 19-22, 2009, Yokohama, Japan
	HaNeul Chon , Taewhan Kim, Timing variation-aware task scheduling and binding for MPSoC, Proceedings of the 2009 Conference on Asia and South Pacific Design Automation, January 19-22, 2009, Yokohama, Japan
	Kelageri Nagaraj , Sandip Kundu, Process variation mitigation via post silicon clock tuning, Proceedings of the 19th ACM Great Lakes symposium on VLSI, May 10-12, 2009, Boston Area, MA, USA
	Cristiano Forzan , Davide Pandini, Statistical static timing analysis: A survey, Integration, the VLSI Journal, v.42 n.3, p.409-435, June, 2009
	Kyung Ki Kim , Yong-Bin Kim, Statistical timing and leakage power analysis of PD-SOI digital circuits, Analog Integrated Circuits and Signal Processing, v.60 n.1-2, p.127-136, August 2009
	Michael Orshansky , Wei-Shen Wang, Statistical analysis of circuit timing using majorization, Communications of the ACM, v.52 n.8, August 2009
	Chin-Cheng Kuo , Meng-Jung Lee , Chien-Nan Liu , Ching-Ji Huang, Fast statistical analysis of process variation effects using accurate PLL behavioral models, IEEE Transactions on Circuits and Systems Part I: Regular Papers, v.56 n.6, p.1160-1172, June 2009
	Khaled R. Heloue , Navid Azizi , Farid N. Najm, Full-chip model for leakage-current estimation considering within-die correlation, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, v.28 n.6, p.874-887, June 2009
	Lerong Cheng , Jinjun Xiong , Lei He, Non-Gaussian statistical timing analysis using second-order polynomial fitting, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, v.28 n.1, p.130-140, January 2009
	Zhuo Feng , Peng Li , Yaping Zhan, An on-the-fly parameter dimension reduction approach to fast second-order statistical static timing analysis, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, v.28 n.1, p.141-153, January 2009