Power-Optimal Simultaneous Buffer Insertion/Sizing and Wire Sizing

ABSTRACT

This paper studies the problems of minimizing power dissipationof an interconnect wire by simultaneously considering buffer insertion/sizing and wire sizing (BISWS). We consider two cases, namely minimizing power dissipation with optimal delay constraints, and minimizing power dissipation with a given delay penalty.We derive closed form optimal solutions for both cases. Theseclosed form solutions can be used to efficiently estimate the powerdissipation in the early stages of the VLSI designs. We observe thatthe power dissipation can be much different even with the sameoptimal delay.

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.4 INPUT/OUTPUT AND DATA COMMUNICATIONS
      B.4.3 Interconnections (subsystems)
          Subjects: Topology (e.g., bus, point-to-point)

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration)
  B.8 Performance and Reliability
      B.8.2 Performance Analysis and Design Aids

General Terms:
Algorithms, Design, Performance