A Trade-off Oriented Placement Tool

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A Trade-off Oriented Placement Tool

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International Conference on Computer Aided Design archive
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design table of contents

Page: 467

Year of Publication: 2003

ISBN ~ ISSN:1092-3152 , 1-58113-762-1

Authors

Huaiyu Xu	University of California, Los Angeles
Maogang Wang	Cadence Design Systems, San Jose, CA
Bo-Kyung Choi	University of California, Los Angeles
Majid Sarrafzadeh	University of California, Los Angeles

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

IEEE Computer Society Washington, DC, USA

Bibliometrics

Downloads (6 Weeks): 0, Downloads (12 Months): 6, Citation Count: 3

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abstract references cited by index terms collaborative colleagues

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DOI Bookmark:	10.1109/ICCAD.2003.23

ABSTRACT

High quality placement results are always produced at the cost ofsignificant runtimes. In this paper, we study the trade-offbetween the overall quality and the runtime for standard-cellplacement problems. We implemented and studied a class ofschemes to achieve the runtime vs. quality trade-off. Wedeveloped a new trade-off oriented placement tool (TOOP)which is controlled by decision trees. TOOP can adjust itselfbased on user's requests and netlist properties. Compared toCadence QPlace, even the fastest mode of TOOP (lowest quality)can produce placements with similar or better layout. TOOP alsoshows much stronger ability to produce routable placement whencompared to Capo.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Saurabh N. Adya , Mehmet C. Yildiz , Igor L. Markov , Paul G. Villarrubia , Phiroze N. Parakh , Patrick H. Madden, Benchmarking for large-scale placement and beyond, Proceedings of the 2003 international symposium on Physical design, April 06-09, 2003, Monterey, CA, USA [doi>10.1145/640000.640022]
	2	Andrew E. Caldwell , Andrew B. Kahng , Igor L. Markov, Can recursive bisection alone produce routable placements?, Proceedings of the 37th conference on Design automation, p.477-482, June 05-09, 2000, Los Angeles, California, United States [doi>10.1145/337292.337549]
	3	Chin-Chih Chang , Jason Cong , Min Xie, Optimality and scalability study of existing placement algorithms, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan [doi>10.1145/1119772.1119914]
	4	Sung Woo Hur , John Lillis, Mongrel: hybrid techniques for standard cell placement, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
	5	Maogang Wang , Xiaojian Yang , Majid Sarrafzadeh, Dragon2000: standard-cell placement tool for large industry circuits, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
	6	Xiaojian Yang , Ryan Kastner , Majid Sarrafzadeh, Congestion reduction during placement based on integer programming, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	7	Mehmet Can Yildiz , Patrick H. Madden, Improved cut sequences for partitioning based placement, Proceedings of the 38th conference on Design automation, p.776-779, June 2001, Las Vegas, Nevada, United States [doi>10.1145/378239.379064]

CITED BY 3

	Jin Guo , Antonis Papanikolaou , Pol Marchal , Francky Catthoor, Energy/area/delay trade-offs in the physical design of on-chip segmented bus architecture, Proceedings of the international workshop on System-level interconnect prediction, March 04-05, 2006, Munich, Germany
	Maogang Wang , Abhishek Ranjan , Salil Raje, Multi-Million Gate FPGA Physical Design Challenges, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.891, November 09-13, 2003
	Jin Guo , Antonis Papanikolaou , Hao Zhang , Francky Catthoor, Energy/area/delay tradeoffs in the physical design of on-chip segmented bus architecture, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.8, p.941-944, August 2007