Cache Optimization For Embedded Processor Cores: An Analytical Approach

ABSTRACT

Embedded microprocessor cores are increasingly beingused in embedded and mobile devices. The softwarerunning on these embedded microprocessor cores is often apriori known, thus, there is an opportunity for customizingthe cache subsystem for improved performance. In thiswork, we propose an efficient algorithm to directly computecache parameters satisfying desired performance criteria.Our approach avoids simulation and exhaustiveexploration, and, instead, relies on an exact algorithmicapproach. We demonstrate the feasibility of our algorithmby applying it to a large number of embedded systembenchmarks.

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INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.3 SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS
      Subjects: Real-time and embedded systems

Additional Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.3 Other Architecture Styles
          Subjects: Cellular architecture (e.g., mobile)
  C.3 SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS
      Subjects: Microprocessor/microcomputer applications

General Terms:
Algorithms, Design, Performance

Keywords:
Cache Optimization, Core-Based Design, Design Space Exploration, System-on-a-Chip