Vectorless Analysis of Supply Noise Induced Delay Variation

ABSTRACT

The impact of power supply integrity on a design has become acritical issue, not only for functional verification, but also for performanceverification. Traditional analysis has typically applied a worstcase voltage drop at all points along a circuit path which leads to avery conservative analysis. We also show that in certain cases, thetraditional analysis can be optimistic, since it ignores the possibilityof voltage shifts between driver and receiver gates. In this paper, wepropose a new analysis approach for computing the maximum pathdelay under power supply fluctuations. Our analysis is based on theuse of superposition, both spatially across different circuit blocks,and temporally in time. We first present an accurate model of pathdelay variations under supply drops, considering both the effect oflocal supply reduction at individual gates and voltage shifts betweendriver/receiver pairs. We then formulate the path delay maximizationproblem as a constrained linear optimization problem, consideringthe effect of both IR drop and LdI/dt drops. We show how correlationsbetween currents of different circuit blocks can be incorporatedin this formulation using linear constraints. The proposed methodswere implemented and tested on benchmark circuits, including anindustrial power supply grid and we demonstrate a significantimprovement in the worst-case path delay increase.

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
          Subjects: Verification

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
          Subjects: Layout
  B.8 Performance and Reliability
      B.8.1 Reliability, Testing, and Fault-Tolerance

General Terms:
Algorithms, Performance, Verification