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Weibull Based Analytical Waveform Model
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Source International Conference on Computer Aided Design archive
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design table of contents
Page: 161  
Year of Publication: 2003
ISBN ~ ISSN:1092-3152 , 1-58113-762-1
Authors
Chirayu S. Amin  Northwestern Univ., Evanston, IL
Florentin Dartu  Intel Corporation, Hillsboro, OR
Yehea I. Ismail  Northwestern Univ., Evanston, IL
Sponsor
SIGDA: ACM Special Interest Group on Design Automation
Publisher
IEEE Computer Society  Washington, DC, USA
Bibliometrics
Downloads (6 Weeks): 7,   Downloads (12 Months): 27,   Citation Count: 11
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abstract   references   cited by   index terms   collaborative colleagues  

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DOI Bookmark: 10.1109/ICCAD.2003.150

ABSTRACT

Current CMOS technologies are characterized by interconnectlines with increased relative resistance w.r.t. driver outputresistance. Designs generate signal waveshapes that are verydifficult to model using a single parameter model such as thetransition time. In this paper, we present a simple and robustparameter analytical expression for waveform modeling based onthe Weibull cumulative distribution function. The Weibull modelaccurately captures the variety of waveshapes without introducingsignificant runtime overhead and produces results with less than5% error. We also present a fast and simple algorithm to convertwaveforms obtained by circuit simulation to the Weibull model. Amethodology for characterizing gates for the new model is alsopresented. Simulation results for many single and multiple inputgates show errors well below 5%. Our model can be used in amixed environment where some signals may still be characterizedby a single parameter.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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[2] R. B. Hitchcock, G. L. Smith, and D. D. Cheng, "Timing analysis of computer hardware," IBM Journal of Research and Development, Vol. 26, 1982, pp. 100-105.
 
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[3] Miki, Y., Abe, M., and Ogawa, Y., "PCHECK: A delay analysis tool for high performance LSI design," IEEE Custom Integrated Circuits Conference, pp. 267-270, 1995.
 
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[4] Dartu, F. and Pillage, L. T., "Modeling signal waveshapes for empirical CMOS gate delay models," 6th Intl. Workshop PATMOS '96, pp. 57-66, 1996.
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[6] Hayter, A. J., Probability and Statistics for Engineers and Scientists, Second Edition. Duxbury Press, 2002.
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[10] Nocedal, J. and Wright, S., Numerical Optimization. Springer Series in Operations Research, 1999.

CITED BY  11

Collaborative Colleagues:
Chirayu S. Amin: colleagues
Florentin Dartu: colleagues
Yehea I. Ismail: colleagues