High-speed systolic architectures for finite field inversion and division

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High-speed systolic architectures for finite field inversion and division

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Great Lakes Symposium on VLSI archive
Proceedings of the 14th ACM Great Lakes symposium on VLSI table of contents

Boston, MA, USA

SESSION: VLSI design table of contents

Pages: 462 - 465

Year of Publication: 2004

ISBN:1-58113-853-9

Authors

Zhiyuan Yan	Lehigh University, Bethlehem, PA
Dilip V. Sarwate	University of Illinois at Urbana-Champaign, Urbana, IL

Sponsors

ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 2, Downloads (12 Months): 17, Citation Count: 3

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ABSTRACT

Based on a new reformulation of the extended Euclidean algorithm, systolic architectures suitable for VLSI implementations are proposed for finite field inversion and division in this paper. The architectures proposed in this paper can achieve O(m²) area-time complexity, O(m) latency, and critical path delays of two logic gates. These architectures show improved performances when compared with previously proposed architectures.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	K. Araki, I. Fujita, and M.Morisue, "Fast Inverters over Finite Field Based on Euclid 's Algorithm," Trans. of IEICE, vol.72E, no.11, pp.1230--1234, November 1989.
	2	J.-H.Guo and C.-L.Wang, "Hardware-efficient Systolic Architecture for Inversion and Division in GF(2m),"in IEEE Proceedings on Comp ters and Digital Techniques, 1998, pp.272--278.
	3	K.K.Parhi, VLSI Digital Signal Processing Systems, John Wiley and Sons, New York, 1999.
	4	Y.Watanabe, N.Takagi, and K.Takagi, "A VLSI Algorithm for Division in GF(2m)Based on Extended Binary GCD Algorithm,"IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol.E85-A, no.5, pp.994--999, May 2002.
	5	C.H.Wu, C.M.Wu, M.D.Shieh, and Y.T.Wang, "Systolic VLSI Realization of a Nove Iterative Division Algorithm over GF(2m): a High-Speed, Low-Complexity Design," in Proceedings of ISCAS '01, Re-2001, pp.33--36.
	6	Zhiyuan Yan , Dilip V. Sarwate, New Systolic Architectures for Inversion and Division in GF(2^m), IEEE Transactions on Computers, v.52 n.11, p.1514-1519, November 2003
	7	Z.Yan and D.V.Sarwate, "Systolic Architectures for Finite Field Inversion and Division," in Proceedings of ISCAS '02, 2002, pp.789--792.

CITED BY 3

	Zhiyuan Yan , Dilip V. Sarwate, Area-efficient two-dimensional architectures for finite field inversion and division, Proceedings of the 15th ACM Great Lakes symposium on VLSI, April 17-19, 2005, Chicago, Illinois, USA
	Z. Yan , D. V. Sarwate , Z. Liu, High-speed systolic architectures for finite field inversion, Integration, the VLSI Journal, v.38 n.3, p.383-398, January 2005
	Z. Yan , D. V. Sarwate , Z. Liu, Erratum to: "High-speed systolic architectures for finite field inversion" [Integration 38(3) (2005) 383-398], Integration, the VLSI Journal, v.39 n.4, p.474-476, July 2006