An ASIC design for a high speed implementation of the hash function SHA-256 (384, 512)

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An ASIC design for a high speed implementation of the hash function SHA-256 (384, 512)

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Great Lakes Symposium on VLSI archive
Proceedings of the 14th ACM Great Lakes symposium on VLSI table of contents

Boston, MA, USA

POSTER SESSION: Poster session 2 table of contents

Pages: 421 - 425

Year of Publication: 2004

ISBN:1-58113-853-9

Authors

Luigi Dadda	Politecnico di Milano, Milan, Italy and ALaRI-USI, Lugano, Switzerland
Marco Macchetti	Politecnico di Milano, Milan, Italy
Jeff Owen	STMicroelectronics NV, Manno, Switzerland

Sponsors

ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 11, Downloads (12 Months): 61, Citation Count: 3

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ABSTRACT

An implementation of the hash functions SHA-256, 384 and 512 is presented, obtaining a high clock rate through a reduction of the critical path length, both in the Expander and in the Compressor of the hash scheme. The critical path is shown to be the smallest achievable. Synthesis results show that the new scheme can reach a clock rate well exceeding 1 GHz using a 0.13um technology.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	NIST. Announcing the secure hash standard. Federal Information Processing Satndards Publication 180-2, August 2002.
	2	Y. K. Kang, D. W. Kim, T. W. Kwon, and J. R. Choi. An efficient implementation of hash function processor for ipsec. Proceedings of the 3rd Asia-Pacific Conference on ASICs, August 2002.
	3	Luigi Dadda , Marco Macchetti , Jeff Owen, The Design of a High Speed ASIC Unit for the Hash Function SHA-256 (384, 512), Proceedings of the conference on Design, automation and test in Europe, p.30070, February 16-20, 2004
	4	Tim Grembowski , Roar Lien , Kris Gaj , Nghi Nguyen , Peter Bellows , Jaroslav Flidr , Tom Lehman , Brian Schott, Comparative Analysis of the Hardware Implementations of Hash Functions SHA-1 and SHA-512, Proceedings of the 5th International Conference on Information Security, p.75-89, September 30-October 02, 2002
	5	N. Sklavos and O. Koufopavlou. On the hardware implementations of the sha-2(256,384,512) hash functions. Proc. of ISCAS 2003, May 2003.
	6	Kurt K. Ting , Steve C. L. Yuen , K. H. Lee , Philip Heng Wai Leong, An FPGA Based SHA-256 Processor, Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications, p.577-585, September 02-04, 2002
	7	http://www.heliontech.com/core6.htm.

CITED BY 3

	Yong Ki Lee , Herwin Chan , Ingrid Verbauwhede, Design Methodology for Throughput Optimum Architectures of Hash Algorithms of the MD4-class, Journal of Signal Processing Systems, v.53 n.1-2, p.89-102, November 2008
	Ricardo Chaves , Georgi Kuzmanov , Leonel Sousa , Stamatis Vassiliadis, Cost-efficient SHA hardware accelerators, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.16 n.8, p.999-1008, August 2008
	Vikas R. Vasisht , Hsien-Hsin S. Lee, SHARK: Architectural support for autonomic protection against stealth by rootkit exploits, Proceedings of the 2008 41st IEEE/ACM International Symposium on Microarchitecture, p.106-116, November 08-12, 2008