A new test pattern generator for high defect coverage in a BIST environment

ABSTRACT

In this paper we propose a new Test Pattern Generator (TPG) for the detection of realistic faults occurring in CMOS nanometer technologies. The proposed TPG compares favorably to the corresponding already known TPGs with respect to the fault coverage obtained by test sequences of the same length. Another advantage of the proposed TPG is that the same TPG can be used for testing more than one modules in a SOC.

REFERENCES

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.1 Reliability, Testing, and Fault-Tolerance

General Terms:
Design, Experimentation, Reliability

Keywords:
built-in self test, path delay fault, stuck-at fault