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ABSTRACT

The paper presents the design of the Fixed Point Unit (FXU) for the IBM eServer z990 microprocessor (announced in 2Q '03) that runs at 1.2 GHz [2]. The FXU is capable of executing two Register-Memory instructions including arithmetic instructions and a branch instruction in a single cycle. The FXU executes a total of 369 instructions that operate on variable size operands (1 to 256 bytes). The instruction set include decimal arithmetic with multiplies and divides, binary arithmetic, shifts and rotates, loads/stores, branches, long moves, logical operations, convert instructions, and other special instructions. The FXU consists of 64-bit dataflow stack that is custom designed and a control stack that is synthesized. The current FXU is the first superscalar design for the CMOS z-series machines, has a new improved decimal unit, and has for the first time a 16x64 bit binary multiplier.

REFERENCES

• 1: Glenn Hinton et. al, "A 0.18-um CMOS IA-32 Processor With a 4-GHz Integer Execution Unit," IEEE Journal of Solid State Circuits, Vol. 36, No. 11, Nov. 2001.
• 2: T. J. Siegel , E. Pfeffer , J. A. Magee, The IBM eServer z990 microprocessor, IBM Journal of Research and Development, v.48 n.3-4, p.295-309, May 2004
• 3: T. McPherson and et al. "760 MHz G6 S/390 Microprocessor Exploiting Multiple Vt and Copper Interconnects", Solid-State Circuits Conference, Feb. 2000.
• 4: G. Northrop and et. Al "600 MHz G5 S/390 Microprocessor", 1999 International Solid-State Circuits Conference, Feb. 1999, pp. 88--89.
• 5: Timothy . Slegel and et al. "IBM S/390 G5 Microprocessor", 1998 Hot Chips Symposium, Stanford. Aug., 1998.
• 6: F. Busaba, et. al, "The IBM z900 Decimal Arithmetic Unit, "35th Asilomar Conference on Signals, Systems and Computers, Nov. 2001.
• 7: F. Busaba, and et. al, "Designer-Level Logic Verification Using RuleBase, "4th International Workshop of Testing Embedded Core-based System-Chips, Montreal, May 2000.
• 8: A. Chandra , V. Iyengar , D. Jameson , R. Jawalekar , I. Nair , B. Rosen , M. Mullen , J. Yoon , R. Armoni , D. Geist , Y. Wolfsthal, AVPGEN—a test generator for architecture verification, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.3 n.2, p.188-200, June 1995 [doi>10.1109/92.386220]

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.5 COMPUTER SYSTEM IMPLEMENTATION
      C.5.3 Microcomputers
          Subjects: Microprocessors

General Terms:
Design, Performance

Keywords:
microprocessor, superscalar FXU