SET-based nano-circuit simulation and design method using HSPICE

ABSTRACT

This paper presents a simulation and design method for complementary SET-based nano-circuits. A HSPICE behavioral implementation of modified Lientschnig's SET model based on the orthodox theory and the Birth-Death Markov chain is demonstrated and verified with Coulomb characteristics. It shows a reduced CPU time and more compatibility with other SPICE softwares on both Windows and Unix. The design methodology illustrates how to build CMOS-like SET circuits, and based on it, conventional static CMOS circuit design methodologies are all applicable to SET circuit designs. Simulation results show that, for 1M$\Omega$ junction resistance, the power consumption of a SET NAND2 gate is less than 0.3pW, and the propagation delay for a SET XOR2 gate is only 29.8ns while driving a 10aF load.

REFERENCES

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
          Subjects: Simulation

  I. Computing Methodologies
  I.6 SIMULATION AND MODELING
      I.6.5 Model Development

General Terms:
Design

Keywords:
SET circuit design, SET modeling, SET simulation with HSPICE