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Practical slicing and non-slicing block-packing without simulated annealing
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Source Great Lakes Symposium on VLSI archive
Proceedings of the 14th ACM Great Lakes symposium on VLSI table of contents
Boston, MA, USA
SESSION: CAD table of contents
Pages: 282 - 287  
Year of Publication: 2004
ISBN:1-58113-853-9
Authors
Hayward H. Chan  The University of Michigan, Ann Arbor, MI
Igor L. Markov  The University of Michigan, Ann Arbor, MI
Sponsors
ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 3,   Downloads (12 Months): 25,   Citation Count: 3
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ABSTRACT

We propose a new floorplanner BloBB based on multi-level branch-and-bound. It is competitive with annealers in terms of runtime and solution quality. We empirically quantify the gap between optimal slicing and non-slicing floorplans by comparing optimal packings and best seen results. Optimal slicing and non-slicing packings for apte, xerox and hp are reported. We also discover that the soft versions of all MCNC benchmarks, except for apte, and all GSRC benchmarks can be packed with zero dead-space.Additionally, realistic floorplans often have blocks with similar dimensions, if design blocks, such as memories, are reused. We show that this greatly reduces the complexity of black-packing.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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S.N. Adya, I.L. Markov, "Fixed-outline Floorplanning: Enabling Hierarchical Design," IEEE Trans. on VLSI 11(6), pp. 1120-1135, 2003. http://vlsicad.eecs.umich.edu/BK/parquet/
 
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A.E. Caldwell, A.B. Kahng, and I.L. Markov, "Optimal Partitioners and End-case Placers for Standard-cell Layout," IEEE Trans. on CAD, 19(11), pp. 1304--1314, 2000.
 
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H.H. Chan and I.L. Markov, "Practical Slicing and Non-slicing Block-Packing without Simulated Annealing," CSE-TR-487-04, The University of Michigan, 2004.
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I. Mandoiu, "Multi-Project Reticle Floorplanning and Wafer Dicing," to appear in ISPD 2004.
 
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H. Murata et al., "VLSI Module Placement Based on Rectangle-Packing by the Sequence-Pair," IEEE Trans on CAD 15(12), pp. 1518--1524, 1996.
 
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Collaborative Colleagues:
Hayward H. Chan: colleagues
Igor L. Markov: colleagues