| Practical slicing and non-slicing block-packing without simulated annealing |
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Great Lakes Symposium on VLSI
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Proceedings of the 14th ACM Great Lakes symposium on VLSI
table of contents
Boston, MA, USA
Pages: 282 - 287
Year of Publication: 2004
ISBN:1-58113-853-9
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Downloads (6 Weeks): 3, Downloads (12 Months): 25, Citation Count: 3
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ABSTRACT
We propose a new floorplanner BloBB based on multi-level branch-and-bound. It is competitive with annealers in terms of runtime and solution quality. We empirically quantify the gap between optimal slicing and non-slicing floorplans by comparing optimal packings and best seen results. Optimal slicing and non-slicing packings for apte, xerox and hp are reported. We also discover that the soft versions of all MCNC benchmarks, except for apte, and all GSRC benchmarks can be packed with zero dead-space.Additionally, realistic floorplans often have blocks with similar dimensions, if design blocks, such as memories, are reused. We show that this greatly reduces the complexity of black-packing.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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H.H. Chan and I.L. Markov, "Practical Slicing and Non-slicing Block-Packing without Simulated Annealing," CSE-TR-487-04, The University of Michigan, 2004.
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I. Mandoiu, "Multi-Project Reticle Floorplanning and Wafer Dicing," to appear in ISPD 2004.
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Hidetoshi Onodera , Yo Taniguchi , Keikichi Tamaru, Branch-and-bound placement for building block layout, Proceedings of the 28th conference on ACM/IEEE design automation, p.433-439, June 17-22, 1991, San Francisco, California, United States
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CITED BY 3
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Nathan A. Carr , Jared Hoberock , Keenan Crane , John C. Hart, Rectangular multi-chart geometry images, Proceedings of the fourth Eurographics symposium on Geometry processing, June 26-28, 2006, Cagliari, Sardinia, Italy
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