Power-efficient ASIC synthesis of cryptographic sboxes

ABSTRACT

In this paper we present a novel methodology that can be used to design efficient hardware structures for a certain class of combinatorial functions. The methodology is primarily intended to achieve low-power synthesis of non-linear one-to-one functions on ASIC technology libraries and fits well for the synthesis of small cryptographic substitution box (Sbox) functional components; the latter are found in most secret key cryptographic algorithms, and usually represent their most relevant part in terms of required computational power. We also describe an extension that allows us to apply the method to general vectorial Boolean functions.

REFERENCES

• 1: AES homepage, available at http://csrc.nist.gov/aes.
• 2: J. Daemen and V. Rijmen. AES proposal: Rijndael. NIST AES Proposal, June 1998.
• 3: Carlisle Adams , Stafford Tavares, The structured design of cryptographically good s-boxes, Journal of Cryptology, v.3 n.1, p.27-41, 1990
• 4: L. O'Connor. An analysis of a class of algorithms for S-box construction. Journal of Cryptology, 7(3):133--151, 1994.
• 5: Sasan Iman , Massoud Pedram, Multi-level network optimization for low power, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.372-377, November 06-10, 1994, San Jose, California, United States
• 6: Sasan Iman , Massoud Pedram, Two-level logic minimization for low power, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.433-438, November 05-09, 1995, San Jose, California, United States
• 7: L. Xiao and H. M. Heys. Hardware design and analysis of block cipher components. In Proc. 5th ICISC, 2002.
• 8: B. S. Amrutur and M. A. Horowitz. Fast low-power decoders for rams. IEEE Journal of Solid State Circuits, 36(10):1506--1515, oct 2001.
• 9: G. Marsaglia. Mother of all pseudo random number generator, http://www.agner.org/random/mother/.
• 10: N. Sklavos , O. Koufopavlou, Architectures and VLSI Implementations of the AES-Proposal Rijndael, IEEE Transactions on Computers, v.51 n.12, p.1454-1459, December 2002 [doi>10.1109/TC.2002.1146712]
• 11: Atri Rudra , Pradeep K. Dubey , Charanjit S. Jutla , Vijay Kumar , Josyula R. Rao , Pankaj Rohatgi, Efficient Rijndael Encryption Implementation with Composite Field Arithmetic, Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems, p.171-184, May 14-16, 2001
• 12: M. Macchetti and G. Bertoni. Hardware implementation of the rijndael sbox: a case study. ST Journal of System Research, (0):84--91, jul 2003.
• 13: Sumio Morioka , Akashi Satoh, An Optimized S-Box Circuit Architecture for Low Power AES Design, Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems, p.172-186, August 13-15, 2002

INDEX TERMS

Primary Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.1 Design Styles
          Subjects: Combinational logic

General Terms:
Design, Performance, Security

Keywords:
S-box implementation, cryptography, low power logic