A high level language for pre-layout extraction in parasite-aware analog circuit synthesis

ABSTRACT

This paper presents a high-level language MSL, for the specification of parameterized, topology-specific circuit extractors. Upon compilation, the MSL program yields an executable module which generates the extracted circuit containing parasitics, passive and active devices when given specific sizes. In contrast to traditional post-layout extraction, this is done without ever generating a layout. We call this pre-layout extraction. Pre-layout extraction is much faster than post-layout extraction and is highly suited for use in layout-aware circuit sizing programs. MSL can also be used for the specification of parameterized layout generators. Thus, although a concrete layout is never generated during pre-extraction, the extracted circuit is very much influenced by the symbolic placement and routing specified in the layout generation part of the MSL program. This ensures that the pre-layout extraction process yields the same results as post-layout extraction. Being a high-level language based approach, users can tune pre-layout extraction to a desired level of accuracy by modeling selected parasitics and ignoring others. This ability helps further speed up the circuit sizing process up to a factor varying from 2.5 to 4.5 compared to layout-inclusive synthesis methodologies.

REFERENCES

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INDEX TERMS

Primary Classification:
  J. Computer Applications
  J.6 COMPUTER-AIDED ENGINEERING
      Subjects: Computer-aided design (CAD)

General Terms:
Design, Languages

Keywords:
MSL, analog VLSI, parasitics, pre-layout extraction