Mitigating static power in current-sensed interconnects

ABSTRACT

Interconnects are an increasing concern in recent years, resulting in novel techniques such as current sensing. However these techniques must be designed to tradeoff delay and both dynamic and static power consumption. This paper presents an innovative approach to reduce static power in differential current-sensed interconnects. This system uses a self-timed shut-off system to reduce static currents used to bias the current sense amplifier. Results indicated that the self timed shut-off system reduced static power by 23.4% for a 10mm line in 250nm technology with no overhead in performance. On an average it reduced static power by 9.7% for 4mm-9mm lines over 180nm, 130nm, 100nm and 65nm technologies and 6% from 10mm-15mm line over the same set of technologies as before. Physical design of the system was implemented in 250nm technology along with the implementation of a test circuit, ready to be fabricated. Extensions of this shut-off mechanism may be useful for mitigating leakage power in a variety of interconnect circuits.

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.m Miscellaneous

General Terms:
Design, Performance

Keywords:
interconnect circuits, self-timed systems, static power