A noise optimization technique for codesign of CMOS radio-frequency low noise amplifiers and low-quality spiral inductors

ABSTRACT

Series resistance associated with inductor is usually ignored in noise optimization for CMOS low noise amplifiers (LNAs). With low-quality on-chip inductor the series resistance, however, degrades input matching and increases noise figure considerably. The LNA design is complicated by the fact that the series resistance varies with inductance in some specific pattern determined by physical implementation for on-chip inductor. This paper presents a novel noise optimization technique for the codesign of LNA and low-quality square spiral inductor. Theoretical derivation is given to model the tradeoff between thermal noise of series resistance and transistor channel noise for minimizing noise figure. A figure-of-merit (FOM) is proposed to characterize the relation between quality factor and effective inductance for square spiral inductor. The codesign of LNA and inductor is done by performing noise optimization for constant FOM. Design procedure is developed and validated by post-layout simulation in AMI 0.6um CMOS process with Cadence SpectreRF and Berkeley ASITIC tools.

REFERENCES

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles

General Terms:
Design

Keywords:
CMOS, LNA, RF, inductance