Self-resetting stage logic pipelines

ABSTRACT

In this paper, we present a novel synchronization approach to support data flow in clockless designs using single-rail encoding. This approach is based on self-resetting stage logic in which a pipeline stage resets itself before starting the next execution cycle. As such, a stage goes through a reset phase when its output is null, and an evaluate phase when its output is the result of the evaluation of its inputs. To insure correct operation, a pipeline stage is ready to absorb inputs from a previous stage if it is in the reset phase. As a result, data flow from one stage to another when the preceding stage is in the evaluate phase while the following stage is in the reset phase. To support this data flow, a latch-based synchronization mechanism is proposed. This mechanism yields an efficient and simple uni-directional handshaking scheme between stages that allows for easy implementation. This handshaking scheme is extended to handle the join and forks of data flows encountered in non-linear pipelines. A concept design of a four-bit 16-stage pipeline is presented to illustrate the inner workings of self-resetting stage logic and its data-flow synchronization mechanism. The pipeline performance is examined through a detailed signal timing analysis. This analysis reveals some insights on how the duration of the evaluate phase gradually increases while the duration of the reset phase and the latch enable gradually decreases toward the left stages of the pipeline. This gradual decrease in the duration of the enable of the latches between stages is used to derive a bound on the maximum possible depth of the pipeline.

REFERENCES

• 1: Tyler J. Thorp , Gin S. Yee , Carl M. Sechen, Design and synthesis of dynamic circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.1, p.141-149, February 2003 [doi>10.1109/TVLSI.2002.800518]
• 2: G. Jung, V. Sudarajan, and G. E. Sobelman, "A robust self-resetting CMOS 32-bit parallel adder," IEEE International Symposium on Circuits and Systems, 2002, pp. I/473--I/476.
• 3: W. Hwang, G. D. Gristede, P. Sanda, S. Y. Wang, and F. Heidel, "Implementation of a self-resetting CMOS 64-bit parallel adder with enhanced testability," IEEE Journal of Solid-State Circuits, vol. 34, pp. 1108--1117, Aug. 1999.
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INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration)

Additional Classification:
  B. Hardware
  B.2 ARITHMETIC AND LOGIC STRUCTURES
      B.2.1 Design Styles
          Subjects: Pipeline
  B.4 INPUT/OUTPUT AND DATA COMMUNICATIONS
      B.4.3 Interconnections (subsystems)
          Subjects: Asynchronous/synchronous operation

General Terms:
Design, Performance

Keywords:
asynchronous, clockless, pipeline, self-resetting