Leakage power minimization for the synthesis of parallel multiplier circuits

ABSTRACT

This paper presents a new approach to the synthesis of parallel multiplier circuits with an objective of minimizing leakage power consumption under circuit timing constraint. Our leakage power optimization is based on the use of dual-threshold voltage (Vt) technology. From experiments using a set of benchmark designs, it is shown that the approach is quite effective.

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.3 Design Aids

General Terms:
Algorithms, Design

Keywords:
power optimization, synthesis