Leakage current reduction by new technique in standby mode

ABSTRACT

In this paper, a new approach for reducing the subthreshold leakage current of digital circuits is proposed. It does not use a multi-threshold process technique which is more expensive. The technique which makes to use of a new variable supply voltage oscillator, combines the ideas of both Standby Leakage Control Using Transistor Stacks (SRB) and variable threshold (VT) methods. In this technique compared to the Leakage Control Using Transistor Stacks method, the subthreshold current decreases three times. In addition, leakage current monitor (LCM) and its related circuits which are used in VT techniques are not required here. This makes the proposed technique more power and area efficient.

REFERENCES

• 1: T. Kuoda, T. Fujita, S. Mita, T. Nagamatu, S.Yoshioka, K. Suzuki, F.Sano, M. Norishima, M. Murota, M. Kako, M. Kinugawa, M. Kakumu, and T. Sakurai, "A 0.9 V 150 MHz 10 mW 4 mm2 2-D Discrete Cosine Transform Core Processor with Variable Threshold-voltage (VT) Scheme," IEEE J. Solid -State Circuits, vol. 31, no. 11, pp. 1770--1779, Nov. 1996.
• 2: T. Kuroda, T. Fujita, T. Nagamatu, S. Yoshioka, T. Sei, K. Matsuo, Y. Hamura, T. Mori, M. Murota, M. Kakuma, and T. Sakurai, " A High-speed Low-power 0.3 μm CMOS Gate Array with Variable Threshold Voltage (VT) Scheme," Proc. CICC'96, pp. 53--56, May 1996.
• 3: T. Kawahara, M. Horiguchi, Y. Kawajiri, G. Kitsukawa, T. Kure and M. Aoki "Subthreshold Current Reduction for Decoded-Driver by Self-Reverse Biasing" IEEE J. Solid -State Circuits, vol. 28, no. 11, pp. 1136--1144, Nov. 1993.
• 4: James Kao , Anantha Chandrakasan , Dimitri Antoniadis, Transistor sizing issues and tool for multi-threshold CMOS technology, Proceedings of the 34th annual conference on Design automation, p.409-414, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266182]
• 5: H. Kawaguchi, K. Nose, and T. Sakurai, "A Super Cut-Off CMOS (SCCMOS) Scheme for 0.5-v Supply Voltage with Picoampere Stand-by Current," IEEE J. Solid State Circuits, vol. 35, no. 10 Oct 2000.
• 6: Berkeley Predictive Technology Model (BPTM), "http://www.device.eecs.berkeley.edu/~ptm.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles

General Terms:
Design

Keywords:
digital integrated circuits, leakage current, low power, static power, subthreshold current