| |
1
|
1. ISSCC Digest of Technical Papers XXII, February 1979.
|
| |
2
|
2. ISSCC Digest of Technical Papers XXIII, February 1980.
|
| |
3
|
3. Strauss, W. Forward Concepts. Quote supplied for this article.
|
| |
4
|
4. Tredennick, N. The death of the DSP. June 6, 2000; see: http://www.ttivanguard.com/dublin/dspdealth.pdf.
|
| |
5
|
5. Input samples are memory based rather than from I/O registers because they are reused cyclically.
|
| |
6
|
6. Howard Aiken, a WWII computer pioneer, classified processors according to the number of buses used. According to this classification, DSPs aren't "modified" Harvard architectures. They are, in fact, "Class III" Aiken machines.
|
| |
7
|
7. How do you pack over 130 instructions into 16 bits? With numerous special registers.
|
| |
8
|
8. The next-generation 'C64xx restored multiply-accumulates.
|
| |
9
|
9. Speech recognition isn't included in the tally of the worst-case load because it's an offline function.
|
| |
10
|
10. Probell, J. Improving application performance with instruction set extensions to embedded processors. DesignCon 2004; see: http://www.ultradatacorp.com/ publications.html.
|
| |
11
|
11. Yoshida, J. TI and UB Video get a jump on H.264 decoding. EE Times (December 2, 2002); http: //www.eetimes.com/semi/news/OEG20021202S0048.
|
| |
12
|
|
| |
13
|
13. See reference 4.
|