Placement driven synthesis case studies on two sets of two chips: hierarchical and flat

ABSTRACT

In this paper I describe two sets of two large ASIC chips that have recently been processed from netlist to final design by the Semi-Custom Design Team part of IBM's World-Wide Design Center. I address issues such as why the parts were selected for special handling, the issues with the designs that required custom engineering, and the special techniques used in placement driven synthesis that enabled successful completion of the designs.

INDEX TERMS

Primary Classification:
  J. Computer Applications
  J.6 COMPUTER-AIDED ENGINEERING
      Subjects: Computer-aided design (CAD)

General Terms:
Algorithms, Design, Economics, Performance

Keywords:
application specific integrated circuit (ASIC), netlist, placement, register transfer level (RTL), static timing analysis (STA), synthesis