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ABSTRACT
We present an overview of a new monolithic fabrication technology known as three-dimensional integration. 3D integration refers to any process by which multiple conventional device layers may be stacked and electrically interconnected. By combining state-of-the-art single-wafer integration with a high-density inter-wafer interconnect, our 3D integration process is capable of providing improved circuit performance in terms of metrics such as wire length, area, timing, and energy consumption. In this paper, we will discuss the overall 3D integration process flow, as well as specific technological challenges and the issues they present to circuit designers. We will also describe how these issues may be tackled during the placement, routing, and layout stages of physical design. Finally, we will present some performance results that may be obtained by integrating circuits in three dimensions.
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CITED BY 16
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Zhuoyuan Li , Xianlong Hong , Qiang Zhou , Shan Zeng , Jinian Bian , Hannah Yang , Vijay Pitchumani , Chung-Kuan Cheng, Integrating dynamic thermal via planning with 3D floorplanning algorithm, Proceedings of the 2006 international symposium on Physical design, April 09-12, 2006, San Jose, California, USA
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Tan Yan , Qing Dong , Yasuhiro Takashima , Yoji Kajitani, How does partitioning matter for 3D floorplanning?, Proceedings of the 16th ACM Great Lakes symposium on VLSI, April 30-May 01, 2006, Philadelphia, PA, USA
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Zuoyuan Li , Xianlong Hong , Qiang Zhou , Jinian Bian , Hannah H. Yang , Vijay Pitchumani, Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.11 n.2, p.325-345, April 2006
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Feihui Li , Chrysostomos Nicopoulos , Thomas Richardson , Yuan Xie , Vijaykrishnan Narayanan , Mahmut Kandemir, Design and Management of 3D Chip Multiprocessors Using Network-in-Memory, ACM SIGARCH Computer Architecture News, v.34 n.2, p.130-141, May 2006
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Xin Li , Yuchun Ma , Xianlong Hong , Sheqin Dong , Jason Cong, LP based white space redistribution for thermal via planning and performance optimization in 3D ICs, Proceedings of the 2008 conference on Asia and South Pacific design automation, January 21-24, 2008, Seoul, Korea
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Dongkook Park , Soumya Eachempati , Reetuparna Das , Asit K. Mishra , Yuan Xie , N. Vijaykrishnan , Chita R. Das, MIRA: A Multi-layered On-Chip Interconnect Router Architecture, ACM SIGARCH Computer Architecture News, v.36 n.3, p.251-261, June 2008
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