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ABSTRACT
Net weighting is a key technique in large scale timing driven placement, which plays a crucial role for deep submicron physical synthesis and timing closure. A popular way to assign net weight is based on the slack of the nets, trying to minimize the worst negative slack (WNS) for the entire circuit. While WNS is an important optimization metric, another figure of merit (FOM), defined as the total slack difference compared to a certain slack threshold for all timing end points, is of equivalent importance to measure the overall timing closure result for highly complex modern ASIC and microprocessor designs. In this paper, we perform a comprehensive analysis of the slack and FOM sensitivities to the net weight, and propose a new net weighting scheme based on the slack and FOM sensitivities. Such sensitivity analysis implicitly takes potential physical synthesis effect into consideration. Experiment results on a set of industrial circuits are promising for both stand-alone timing driven placement and physical synthesis afterwards.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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1
|
Semiconductor Industry Association, International Technology Roadmap for Semiconductors, 2003, http://public.itrs.net/.
|
 |
2
|
|
 |
3
|
Wilm E. Donath , Reini J. Norman , Bhuwan K. Agrawal , Stephen E. Bello , Sang Yong Han , Jerome M. Kurtzberg , Paul Lowy , Roger I. McMillan, Timing driven placement using complete path delays, Proceedings of the 27th ACM/IEEE conference on Design automation, p.84-89, June 24-27, 1990, Orlando, Florida, United States
[doi> 10.1145/123186.123232]
|
| |
4
|
A. Srinivasan, K. Chaudhary, and E. S. Kuh, "Ritual: A performance driven placement algorithm for small cell ics," in Proc. Int. Conf. on Computer Aided Design, pp. 48--51, 1991.
|
| |
5
|
T. Gao , P. M. Vaidya , C. L. Liu, A performance driven macro-cell placement algorithm, Proceedings of the 29th ACM/IEEE conference on Design automation, p.147-152, June 08-12, 1992, Anaheim, California, United States
|
 |
6
|
|
| |
7
|
B. M. Riess and G. G. Ettelt, "SPEED: fast and efficient timing driven placement," in Proc. IEEE Int. Symp. on Circuits and Systems, pp. 377--380, 1995.
|
| |
8
|
M. Marek-Sadowska and S. P. Lin, "Timing driven placement," in Proc. Int. Conf. on Computer Aided Design, pp. 94--97, 1989.
|
 |
9
|
|
 |
10
|
Alexander Marquardt , Vaughn Betz , Jonathan Rose, Timing-driven placement for FPGAs, Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays, p.203-213, February 10-11, 2000, Monterey, California, United States
[doi> 10.1145/329166.329208]
|
 |
11
|
|
 |
12
|
Karthik Rajagopal , Tal Shaked , Yegna Parasuram , Tung Cao , Amit Chowdhary , Bill Halpin, Timing driven force directed placement with physical net constraints, Proceedings of the 2003 international symposium on Physical design, April 06-09, 2003, Monterey, CA, USA
[doi> 10.1145/640000.640016]
|
| |
13
|
J. Kleinhans, G. Sigl, F. M. Johannes, and K. Antreich, "GORDIAN: VLSI placement by quadratic programming and slicing optimization," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. CAD-10, pp. 356--365, Mar. 1991.
|
 |
14
|
|
 |
15
|
Wilm Donath , Prabhakar Kudva , Leon Stok , Lakshmi Reddy , Andrew Sullivan , Kanad Chakraborty , Paul Villarrubia, Transformational placement and synthesis, Proceedings of the conference on Design, automation and test in Europe, p.194-201, March 27-30, 2000, Paris, France
[doi> 10.1145/343647.343732]
|
 |
16
|
|
 |
17
|
Charles J. Alpert , Anirudh Devgan , Stephen T. Quay, Buffer insertion for noise and delay optimization, Proceedings of the 35th annual conference on Design automation, p.362-367, June 15-19, 1998, San Francisco, California, United States
[doi> 10.1145/277044.277145]
|
| |
18
|
W. C. Elmore, "The transient response of damped linear networks with particular regard to wide-band amplifiers," Journal of Applied Physics, vol. 19, pp. 55--63, Jan. 1948.
|
| |
19
|
|
| |
20
|
P. Villarrubia, G. Nusbaum, R. Masleid, and P. T. Patel, "IBM RISC chip design methodology," in Proc. IEEE Int. Conf. on Computer Design, pp. 143--147, 1989.
|
| |
21
|
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CITED BY 9
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Zhong Xiu , David A. Papa , Philip Chong , Christoph Albrecht , Andreas Kuehlmann , Rob A. Rutenbar , Igor L. Markov, Early research experience with OpenAccess gear: an open source development environment for physical design, Proceedings of the 2005 international symposium on Physical design, April 03-06, 2005, San Francisco, California, USA
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Haoxing Ren , David Z. Pan , Charles J. Alpert , Paul Villarrubia, Diffusion-based placement migration, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
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Tao Luo , David A. Papa , Zhuo Li , C. N. Sze , Charles J. Alpert , David Z. Pan, Pyramids: an efficient computational geometry-based approach for timing-driven placement, Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design, November 10-13, 2008, San Jose, California
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