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Temperature-aware microarchitecture: Modeling and implementation
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Volume 1 ,  Issue 1  (March 2004) table of contents
Pages: 94 - 125  
Year of Publication: 2004
ISSN:1544-3566
Authors
Kevin Skadron  University of Virginia, Charlottesville, VA
Mircea R. Stan  University of Virginia, Charlottesville, VA
Karthik Sankaranarayanan  University of Virginia, Charlottesville, VA
Wei Huang  University of Virginia, Charlottesville, VA
Sivakumar Velusamy  University of Virginia, Charlottesville, VA
David Tarjan  University of Virginia, Charlottesville, VA
Publisher
ACM  New York, NY, USA
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ABSTRACT

With cooling costs rising exponentially, designing cooling solutions for worst-case power dissipation is prohibitively expensive. Chips that can autonomously modify their execution and power-dissipation characteristics permit the use of lower-cost cooling solutions while still guaranteeing safe temperature regulation. Evaluating techniques for this dynamic thermal management (DTM), however, requires a thermal model that is practical for architectural studies.This paper describes HotSpot, an accurate yet fast and practical model based on an equivalent circuit of thermal resistances and capacitances that correspond to microarchitecture blocks and essential aspects of the thermal package. Validation was performed using finite-element simulation. The paper also introduces several effective methods for DTM: "temperature-tracking" frequency scaling, "migrating computation" to spare hardware units, and a "hybrid" policy that combines fetch gating with dynamic voltage scaling. The latter two achieve their performance advantage by exploiting instruction-level parallelism, showing the importance of microarchitecture research in helping control the growth of cooling costs.Modeling temperature at the microarchitecture level also shows that power metrics are poor predictors of temperature, that sensor imprecision has a substantial impact on the performance of DTM, and that the inclusion of lateral resistances for thermal diffusion is important for accuracy.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
Bakker, A. and Huijsing, J. 2000. High-Accuracy CMOS Smart Temperature Sensors. Kluwer Academic, Boston, MA.
 
2
Bannon, P. 2002. Personal communication.
 
3
Benedek, Z., Courtois, B., Farkas, G., Kollár, E., Mir, S., Poppe, A., Rencz, M., Székely, V., and Torki, K. 2001. A scalable multi-functional thermal test chip family: Design and evaluation. Transactions of the ASME, Journal of Electronic Packaging 123, 4 (Dec.), 323--330.
 
4
 
5
6
7
 
8
 
9
 
10
Fleischmann, M. 2000. Crusoe power management: Cutting ×86 operating power through LongRun. In Embedded Processor Forum.
 
11
Garrett, J. and Stan, M. R. 2001. Active threshold compensation circuit for improved performance in cooled CMOS systems. In Proceedings of the International Symposium on Circuits and Systems, 410--413.
 
12
Gunther, S., Binns, F., Carmean, D. M., and Hall, J. C. 2001. Managing the impact of increasing microprocessor power consumption. In Intel Technology Journal.
13
14
 
15
Krum, A. 2000. Thermal management. In The CRC Handbook of Thermal Engineering, F. Kreith, Ed. CRC Press, Boca Raton, FL, 2.1--2.92.
 
16
Lee, S., Song, S., Au, V., and Moran, K. 1995. Constricting/spreading resistance model for electronics packaging. In Proceedings of the ASME/JSME Thermal Engineering Conference, 199--206.
 
17
 
18
 
19
Mahajan, R. 2002. Thermal management of CPUs: A perspective on trends, needs and opportunities. Keynote presentation at the 8th Int'l Workshop on THERMal INvestigations of ICs and Systems.
 
20
Robertson, J. 2002. Intel hints of next-generation security technology for mpus. EE Times.
 
21
Rohou, E. and Smith, M. 1999. Dynamically managing processor temperature and power. In Proceedings of the 2nd Workshop on Feedback-Directed Optimization.
 
22
Sabry, M.-N. 2002. Dynamic compact thermal models: An overview of current and potential advances. In Proceedings of the 8th Int'l Workshop on THERMal INvestigations of ICs and Systems. Invited paper.
 
23
 
24
 
25
 
26
SIA 2001. International Technology Roadmap for Semiconductors. SIA.
 
27
 
28
29
 
30
Skadron, K., Stan, M. R., Huang, W., Velusamy, S., Sankaranarayanan, K., and Tarjan, D. 2003b. Temperature-aware microarchitecture: Extended discussion and results. Tech. Rep. CS-2003-08, University of Virginia Department of Computer Science. Apr.
 
31
Skadron, K., Stan, M. R., Huang, W., Velusamy, S., Sankaranarayanan, K., and Tarjan, D. 2003c. Temperature-aware computer systems: Opportunities and challenges. IEEE Micro 23, 6 (Nov.--Dec.), 52--61.
32
 
33
Stan, M. R., Skadron, K., Barcella, M., Huang, W., Sankaranarayanan, K., and Velusamy, S. 2003. Hotspot: A dynamic compact thermal model at the processor-architecture level. Microelectronics Journal: Circuits and Systems 34, 12 (Dec.), 1153--1165.
 
34
Standard Performance Evaluation Corporation. SPEC CPU2000 Benchmarks. http://www.specbench.org/osg/cpu2000.
 
35
Viswanath, R., Vijay, W., Watwe, A., and Lebonheur, V. 2000. Thermal performance challenges from silicon to systems. Intel Technology Journal.

CITED BY  34

Collaborative Colleagues:
Kevin Skadron: colleagues
Mircea R. Stan: colleagues
Karthik Sankaranarayanan: colleagues
Wei Huang: colleagues
Sivakumar Velusamy: colleagues
David Tarjan: colleagues