MaRS: a macro-pipelined reconfigurable system

ABSTRACT

We introduce MaRS, a reconfigurable, parallel computing engine with special emphasis on scalability, lending itself to the computation-/data-intensive multimedia data processing and wireless communication. Global communication between the processing elements (PEs) in MaRS is performed through a 2D-mesh deadlock-free network, avoiding any concerns due to non-scalable bus-based communication. Additionally, we have developed a second layer of inter-PE connection realized by distributed shared register files and conditional operands, to enhance the performance of MaRS for those applications demanding a tightly coupled PE array. We have modeled and verified a major part of MaRS. The promising results of our preliminary analyses show that MaRS can efficiently be tailored to different applications offering flexible data communication, and high performance.

REFERENCES

• 1: M. Anid , N. Bagherzadeh , N. Tabrizi , H. Du , M. Sanchez-Elez M., Interactive Ray Tracing Using a SIMD Reconfigurable Architecture, Proceedings of the 14th Symposium on Computer Architecture and High Performance Computing (SCAB-PAD'02), p.20, October 28-30, 2002
• 2: Raphaël David , Daniel Chillet , Sébastien Pillement , Olivier Sentieys, DART: A Dynamically Reconfigurable Architecture Dealing with Future Mobile Telecommunications Constraints, Proceedings of the 16th International Parallel and Distributed Processing Symposium, p.108, April 15-19, 2002
• 3: H. Du , M. Sanchez-Elez , N. Tabrizi , N. Bagherzadeh , M. L. Anido , M. Fernandez, Interactive Ray Tracing on Reconfigurable SIMD MorphoSys, Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum, p.20144, March 03-07, 2003
• 4: http://www.motorola.com/SPS/PowerPC/AtiVec/facts/.html
• 5: http://www.analog.com/processors/processors/tigerSHARC/whitePapers/newArch.html
• 6: Amir H. Kamalizad , Chengzhi Pan , Nader Bagherzadeh, Fast Parallel FFT on a Reconfigurable Computation Platform, Proceedings of the 15th Symposium on Computer Architecture and High Performance Computing, p.254, November 10-12, 2003
• 7: Arezou Koohi , Nader Bagherzadeh , Chengzi Pan, A fast parallel reed-solomon decoder on a reconfigurable architecture, Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, October 01-03, 2003, Newport Beach, CA, USA [doi>10.1145/944645.944660]
• 8: Ruby B. Lee, Subword Parallelism with MAX-2, IEEE Micro, v.16 n.4, p.51-59, August 1996 [doi>10.1109/40.526925]
• 9: Lionel M. Ni , Philip K. McKinley, A Survey of Wormhole Routing Techniques in Direct Networks, Computer, v.26 n.2, p.62-76, February 1993 [doi>10.1109/2.191995]
• 10: Chengzhi Pan , Nader Bagherzadeh , Amir Hosein Kamalizad , Arezou Koohi, Design and Analysis of a Programmable Single-Chip Architecture for DVB-T Base-Band Receiver, Proceedings of the conference on Design, Automation and Test in Europe, p.10468, March 03-07, 2003
• 11: Srinivas K. Raman , Vladimir Pentkovski , Jagannath Keshava, Implementing Streaming SIMD Extensions on the Pentium III Processor, IEEE Micro, v.20 n.4, p.47-57, July 2000 [doi>10.1109/40.865866]
• 12: Sanchez-Eleza M., Du H., Tabrizi N., Long Y., Bagherzadeh N., and Fernandez M., "Algorithm optimizations and mapping scheme for interactive ray tracing on a reconfigurable architecture," Journal of Computers & Graphics, Vol. 27, No. 5, 2003.
• 13: Hartej Singh , Ming-Hau Lee , Guangming Lu , Nader Bagherzadeh , Fadi J. Kurdahi , Eliseu M. Chaves Filho, MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications, IEEE Transactions on Computers, v.49 n.5, p.465-481, May 2000 [doi>10.1109/12.859540]
• 14: Hartej Singh , Guangming Lu , Eliseu Filho , Rafael Maestre , Ming-Hau Lee , Fadi Kurdahi , Nader Bagherzadeh, MorphoSys: case study of a reconfigurable computing system targeting multimedia applications, Proceedings of the 37th conference on Design automation, p.573-578, June 05-09, 2000, Los Angeles, California, United States [doi>10.1145/337292.337583]
• 15: Guangming Lu , Ming-Hau Lee , Hartej Singh , Nader Bagherzadeh , Fadi J. Kurdahi , Eliseu M. Chaves Filho, MorphoSys: A Reconfigurable Processor Trageted to High Performance Image Application, Proceedings of the 11 IPPS/SPDP'99 Workshops Held in Conjunction with the 13th International Parallel Processing Symposium and 10th Symposium on Parallel and Distributed Processing, p.661-669, April 12-16, 1999
• 16: Kelvin Sung , Peter Shirley, Ray tracing with the BSP tree, Graphics Gems III, Academic Press Professional, Inc., San Diego, CA, 1992
• 17: Michael Bedford Taylor , Jason Kim , Jason Miller , David Wentzlaff , Fae Ghodrat , Ben Greenwald , Henry Hoffman , Paul Johnson , Jae-Wook Lee , Walter Lee , Albert Ma , Arvind Saraf , Mark Seneski , Nathan Shnidman , Volker Strumpen , Matt Frank , Saman Amarasinghe , Anant Agarwal, The Raw Microprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs, IEEE Micro, v.22 n.2, p.25-35, March 2002 [doi>10.1109/MM.2002.997877]
• 18: Shreekant (Ticky) Thakkar , Tom Huff, Internet Streaming SIMD Extensions, Computer, v.32 n.12, p.26-34, December 1999 [doi>10.1109/2.809248]
• 19: Marc Tremblay , J. Michael O'Connor, UltraSparc I: A Four-Issue Processor Supporting Multimedia, IEEE Micro, v.16 n.2, p.42-50, April 1996 [doi>10.1109/40.491461]

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.2 Multiple Data Stream Architectures (Multiprocessors)
          Subjects: Interconnection architectures (e.g., common bus, multiport memory, crossbar switch)

Additional Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.2 Multiple Data Stream Architectures (Multiprocessors)
          Subjects: Multiple-instruction-stream, multiple-data-stream processors (MIMD)

General Terms:
Design

Keywords:
2D-mesh network, MIMD, computer graphics, multimedia, reconfigurable architectures, wireless communication