Optimal-time multipliers and C-testability

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Optimal-time multipliers and C-testability

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ACM Symposium on Parallel Algorithms and Architectures archive
Proceedings of the second annual ACM symposium on Parallel algorithms and architectures table of contents

Island of Crete, Greece

Pages: 146 - 154

Year of Publication: 1990

ISBN:0-89791-370-1

Authors

B. Becker	Fachbereich 20 - Informatik, Johann Wolfgang Goethe-Universität, D-6000 Frankfurt/Main, West Germany
J. Hartmann	Lehrstuhl Prof. Hotz, Fachbereich 14 - Informatik, Universität des Saarlandes, D-6600 Saarbrücken, West Germany

Sponsors

IEEE-CS : Computer Society
SIGACT: ACM Special Interest Group on Algorithms and Computation Theory
SIGARCH: ACM Special Interest Group on Computer Architecture
CTI : Computer Technology Inst.
EATCS : European Association for Theoretical Computer Science
Computer Tech Inst. : Computer Technology Institute

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 18, Citation Count: 2

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	Be	B. Becker: 'An Easily Testable Optimal- Time VLSI-Multipller', Acta Informatlca 24, 1987, pp. 363-380
	BeKo	Bernd Becker , Reiner Kolla, On the Construction of Optimal Time Adders (Extended Abstract), Proceedings of the 5th Annual Symposium on Theoretical Aspects of Computer Science, p.18-28, February 11-13, 1988
	BeSp	B. Becker, U. Sparmann: 'A Uniform Test Approach for RCC-Adders', Proc. of the 3rd Aegean Workshop of Computing, 1988
	BrKu	R.P. Brent, H.T. Kung: 'A Regular Layout for Parallel Adders', IEEE Trans. on Comp., Vol. C-31, 1~2, pp. 260-264
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	Ho	Sung Je Hong" 'An Easily Testable Parallel Multiplier', Proc. 1988 Int. Symp. Fault- Tolerant Computing, pp. 214-219
	HBKMO	B. Becker , G. Hotz , R. Kolla , P. Molitor , H.-G. Osthof, Hierarchical design based on a calculus of nets, Proceedings of the 24th ACM/IEEE conference on Design automation, p.649-653, June 28-July 01, 1987, Miami Beach, Florida, United States [doi>10.1145/37888.37992]
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	RoRa	M. Robinson, J. Rajski: 'An Algorithmic Branch and Bound Method For PLA Test Pattern Generation', Proc. 1988 Int. Test Conf., pp. 784-795
	SrHa	T. Sridhar, J.P. Hayes: 'Design of Easily Testable Bit-Sliced Systems', IEEE Trans. on Comp., Vol. C-30, 1981, pp. 324-336
	VuLu	J. Vuillemin, W.K. Luk: 'Recursive Implementation of Optimal Time VLSI Integer Multipliers', IFIP Proc. VLSI'83, 1983, pp. 155-168
	Wa	C.S. Wallace: 'A Suggestion for a Fast Multiplier', IEEE Trans. on Electronic Computers, EC-13, 1964, pp. 14-17

CITED BY 2

	Hongzhong Wu, On the assignment complexity of uniform trees, Proceedings of the 1993 international symposium on Symbolic and algebraic computation, p.95-104, July 06-08, 1993, Kiev, Ukraine
	H. Rahaman , J. Mathew , D. K. Pradhan , A. M. Jabir, C-testable bit parallel multipliers over GF(2^m), ACM Transactions on Design Automation of Electronic Systems (TODAES), v.13 n.1, p.1-18, January 2008