Low energy FPGA interconnect design

ABSTRACT

FPGAs are not energy efficient largely due to their programmable, capacitively loaded interconnect. We propose a new low energy FPGA interconnect architecture that is based on low energy switch blocks using Dynamic Threshold CMOS (DTMOS) based switches and an encoded-low swing (EL) technique. The presented case study, based on circuit simulations using SPICE in CMOS 0.13 micron process technology, illustrates that a 41% energy reduction can be achieved compared to the conventional techniques. A one to one comparison between NMOS based switches and the proposed DTMOS based switches reveal that the latter have a 36% lower power-delay product. We also show through a model analysis and circuit simulations that using low swing on interconnect, a timing budget can be met at 30% less energy consumption.