Transistor grouping and metal layer trade-offs in automatic tile layout of FPGAs

ABSTRACT

The physical layout of modern commercial FPGAs is one of the last bastions of manual VLSI layout. Our recent work has automated the FPGA layout process from architectural description to mask-level layout of the repeated FPGA tile. Here we improve on that work using two approaches: 1) by making better choices for the grouping of circuitry into the cells used for the layout and 2) through better allocation of metal. The new groupings improve the FPGA tile area by between 10% and 14%. That, together with the superior metal layer allocation allows us to automatically lay out a very accurate capture of a Xilinx Virtex-E tile that is only 54% to 92% larger than the real thing. With two additional metal layers, our tile area is only 13% larger. In addition, we show that a standard cell implementation is 102% larger than the real Xilinx Virtex-E.