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The gigahertz FPGA: design consideration and applications
Source International Symposium on Field Programmable Gate Arrays archive
Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays table of contents
Monterey, California, USA
POSTER SESSION: Poster abstracts table of contents
Pages: 248 - 248  
Year of Publication: 2004
ISBN:1-58113-829-6
Authors
Jong-Ru Guo  Rensselaer Polytechnic Institute, Troy, NY
C. C. You  Rensselaer Polytechnic Institute, Troy, NY
M. M. Chu  Rensselaer Polytechnic Institute, Troy, NY
R. Heikaus  Rensselaer Polytechnic Institute, Troy, NY
K. Zhou  Rensselaer Polytechnic Institute, Troy, NY
O. Erdogan  Rensselaer Polytechnic Institute, Troy, NY
J. D. Diao  Rensselaer Polytechnic Institute, Troy, NY
B. S. Goda  United State Military Academy, West Point, NY
R. P. Kraft  Rensselaer Polytechnic Institute, Troy, NY
J. F. McDonald  Rensselaer Polytechnic Institute, Troy, NY
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
ACM: Association for Computing Machinery
Publisher
ACM  New York, NY, USA
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ABSTRACT

This paper describes the implementation of a large scale SiGe FPGA that serves as a high speed FPGA test platform. In the FPGA core, 20 x 20 building blocks (Basic Cells) are used to implement logic applications. This chip contains 106 devices including SiGe NPNs and MOSFETs. This chip is fabricating with the IBM SiGe 7HP process with cut off frequency of 120GHz. The target running frequency of this FPGA is 10GHz. Clock repeaters are added for improved clock distribution. A test circuit whose building block cell runs up to 10GHz is fabricated and measured by the same process. Future work and some potential applications of the SiGe FPGA are also described.

Collaborative Colleagues:
Jong-Ru Guo: colleagues
C. C. You: colleagues
M. M. Chu: colleagues
R. Heikaus: colleagues
K. Zhou: colleagues
O. Erdogan: colleagues
J. D. Diao: colleagues
B. S. Goda: colleagues
R. P. Kraft: colleagues
J. F. McDonald: colleagues