Flexibility measurement of domain-specific reconfigurable hardware

ABSTRACT

Traditional metrics used to compare hardware designs include area, performance, and power. However, these metrics do not form a complete evaluation of reconfigurable hardware. For these designs, flexibility is also a key issue, since it is the flexibility of reconfigurable hardware that allows it to implement a variety of circuits. Despite its importance, there is not yet an established method to measure flexibility. This paper explores the flexibility testing issue for domain-specific reconfigurable architectures. We discuss the concept of flexibility as it pertains to domain-specific architectures, and propose a flexibility testing technique involving synthetic circuit generation. This technique is then used to compare three different domain-specific architecture generation algorithms, demonstrating that the testing can in fact differentiate between architectures of differing levels of flexibility.

REFERENCES

• 1: Katherine Compton , Scott Hauck, Totem: Custom Reconfigurable Array Generation, Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, p.111-119, April 29-May 02, 2001 [doi>10.1109/FCCM.2001.47]
• 2: Katherine Compton , Akshay Sharma , Shawn Phillips , Scott Hauck, Flexible Routing Architecture Generation for Domain-Specific Reconfigurable Subsystems, Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications, p.59-68, September 02-04, 2002
• 3: Darren C. Cronquist , Chris Fisher , Miguel Figueroa , Paul Franklin , Carl Ebeling, Architecture Design of Reconfigurable Pipelined Datapaths, Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI, p.23, March 21-24, 1999
• 4: M. Scott, "The RaPiD Cell Structure", Personal Communications, 2001.
• 5: Joel Darnauer , Wayne Wei-Ming Dai, A method for generating random circuits and its application to routability measurement, Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays, p.66-72, February 11-13, 1996, Monterey, California, United States [doi>10.1145/228370.228380]
• 6: M. Hutton, J. Rose, J. Grossman, and D. Corneil, "Characterization and Parameterized Generation of Synthetic Combinational Benchmark Circuits", IEEE Transactions on CAD, Vol. 17, No. 10, pp. 985--996, October 1998.
• 7: Steven J. E. Wilton , Jonathan Rose , Zvonko Vranesic, Structural analysis and generation of synthetic digital circuits with memory, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.9 n.1, p.223-227, Feb. 2001 [doi>10.1109/92.920838]
• 8: M. Hutton, J. Rose and D. Corneil, "Automatic Generation of Synthetic Sequential Benchmark Circuits", IEEE Transactions on CAD, Vol. 21, No. 8, pp. 928--940, August 2002.
• 9: Katherine Leigh Compton , Scott Hauck, Architecture generation of customized reconfigurable hardware, 2003

INDEX TERMS

Primary Classification:
  B. Hardware
  B.6 LOGIC DESIGN

Additional Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.3 Design Aids
          Subjects: Automatic synthesis
  B.8 Performance and Reliability
      B.8.2 Performance Analysis and Design Aids

General Terms:
Algorithms, Design, Experimentation, Measurement

Keywords:
flexibility, programmable hardware, reconfigurable hardware