Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics

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Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics

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International Symposium on Field Programmable Gate Arrays archive
Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays table of contents

Monterey, California, USA

SESSION: Tools and architectures for power minimization table of contents

Pages: 42 - 50

Year of Publication: 2004

ISBN:1-58113-829-6

Authors

Fei Li	University of California, Los Angeles, CA
Yan Lin	University of California, Los Angeles, CA
Lei He	University of California, Los Angeles, CA
Jason Cong	University of California, Los Angeles, CA

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
ACM: Association for Computing Machinery

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 8, Downloads (12 Months): 80, Citation Count: 25

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ABSTRACT

Traditional FPGAs use uniform supply voltage Vdd and uniform threshold voltage Vt. We propose to use pre-defined dual-Vdd and dual-Vt fabrics to reduce FPGA power. We design FPGA circuits with dual-Vdd/dual-Vt to effectively reduce both dynamic power and leakage power, and define dual-Vdd/dual-Vt FPGA fabrics based on the profiling of benchmark circuits. We further develop CAD algorithms including power-sensitivity based voltage assignment and simulated-annealing based placement to leverage such fabrics. Compared to the conventional fabric using uniform Vdd/Vt at the same target clock frequency, our new fabric using dual Vt achieves 9% to 20% power reduction. However, the pre-defined FPGA fabric using both dual Vdd and dual Vt only achieves on average 2% extra power reduction. It is because that the pre-designed dual-Vdd layout pattern introduces non-negligible performance penalty. Therefore, programmability of supply voltage is needed to achieve significant power saving for dual-Vdd FPGAs. To our best knowledge, it is the first in-depth study on applying both dual-Vdd and dual-Vt to FPGA considering circuits, fabrics and CAD algorithms.

REFERENCES

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CITED BY 25

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	Deming Chen , Jason Cong, Delay optimal low-power circuit clustering for FPGAs with dual supply voltages, Proceedings of the 2004 international symposium on Low power electronics and design, August 09-11, 2004, Newport Beach, California, USA
	Andrea Lodi , Luca Ciccarelli , Roberto Giansante, Combining low-leakage techniques for FPGA routing design, Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays, February 20-22, 2005, Monterey, California, USA
	Yan Lin , Fei Li , Lei He, Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability, Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays, February 20-22, 2005, Monterey, California, USA
	Yan Lin , Lei He, Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Hassan Hassan , Mohab Anis , Mohamed Elmasry, LAP: a logic activity packing methodology for leakage power-tolerant FPGAs, Proceedings of the 2005 international symposium on Low power electronics and design, August 08-10, 2005, San Diego, CA, USA
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	Georges Nabaa , Navid Azizi , Farid N. Najm, An adaptive FPGA architecture with process variation compensation and reduced leakage, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
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	Yan Lin , Yu Hu , Lei He , Vijay Raghunat, An efficient chip-level time slack allocation algorithm for Dual-Vdd FPGA power reduction, Proceedings of the 2006 international symposium on Low power electronics and design, October 04-06, 2006, Tegernsee, Bavaria, Germany
	Akhilesh Kumar , Mohab Anis, An analytical state dependent leakage power model for FPGAs, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
	Maurice Meijer , Rohini Krishnan , Martijn Bennebroek, Energy-efficient FPGA interconnect design, Proceedings of the conference on Design, automation and test in Europe: Designers' forum, March 06-10, 2006, Munich, Germany
	Deming Chen , Jason Cong , Peichen Pan, FPGA Design Automation: A Survey, Foundations and Trends® in Electronic Design Automation, v.1 n.3, p.139-169, January 2006
	Philip Garcia , Katherine Compton , Michael Schulte , Emily Blem , Wenyin Fu, An overview of reconfigurable hardware in embedded systems, EURASIP Journal on Embedded Systems, v.2006 n.1, p.13-13, January 2006
	Fei Li , Yan Lin , Lei He, Vdd programmability to reduce FPGA interconnect power, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.760-765, November 07-11, 2004
	J. H. Anderson , F. N. Najm, Low-power programmable routing circuitry for FPGAs, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.602-609, November 07-11, 2004
	Yu Hu , Yan Lin , Lei He , Tim Tuan, Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.13 n.2, p.1-29, April 2008
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