Active leakage power optimization for FPGAs

ABSTRACT

We consider active leakage power dissipation in FPGAs and present a "no cost" approach for active leakage reduction. It is well-known that the leakage power consumed by a digital CMOS circuit depends strongly on the state of its inputs. Our leakage reduction technique leverages a fundamental property of basic FPGA logic elements (look-up-tables) that allows a logic signal in an FPGA design to be interchanged with its complemented form without any area or delay penalty. We apply this property to select polarities for logic signals so that FPGA hardware structures spend the majority of time in low leakage states. In an experimental study, we optimize active leakage power in circuits mapped into a state-of-the-art 90nm commercial FPGA. Results show that the proposed approach reduces active leakage by 25%, on average.

REFERENCES

• 1: Afshin Abdollahi , Massoud Pedram , Farzan Fallah, Runtime mechanisms for leakage current reduction in CMOS VLSI circuits^1,2, Proceedings of the 2002 international symposium on Low power electronics and design, August 12-14, 2002, Monterey, California, USA [doi>10.1145/566408.566460]
• 2: Mohab Anis , Mohamed Mahmoud , Mohamed Elmasry , Shawki Areibi, Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA [doi>10.1145/513918.514041]
• 3: M.A. Cirit. Estimating dynamic power consumption of CMOS circuits. In IEEE International Conference on Computer-Aided Design, pages 534--537, 1987.
• 4: Varghese George , Jan M. Rabaey, Low-energy FPGAs: architecture and design, Kluwer Academic Publishers, Norwell, MA, 2001
• 5: Rafik S. Guindi , Farid N. Najm, Design Techniques for Gate-Leakage Reduction in CMOS Circuits, Proceedings of the 4th International Symposium on Quality Electronic Design, p.61, March 24-26, 2003
• 6: J.P. Halter and F.N. Najm. A gate level leakage power reduction method for ultra-low-power CMOS circuits. In IEEE Custom Integrated Circuits Conference, pages 475--478, 1997.
• 7: Mark C. Johnson , Dinesh Somasekhar , Lih-Yih Chiou , Kaushik Roy, Leakage control with efficient use of transistor stacks in single threshold CMOS, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.1, p.1-5, 2/1/2002 [doi>10.1109/92.988724]
• 8: James Kao , Siva Narendra , Anantha Chandrakasan, Subthreshold leakage modeling and reduction techniques, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.141-148, November 10-14, 2002, San Jose, California [doi>10.1145/774572.774593]
• 9: A. Keshavarzi , S. Ma , S. Narendra , B. Bloechel , K. Mistry , T. Ghani , S. Borkar , V. De, Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs, Proceedings of the 2001 international symposium on Low power electronics and design, p.207-212, August 2001, Huntington Beach, California, United States [doi>10.1145/383082.383135]
• 10: Chris H. Kim , Jae-Joon Kim , Saibal Mukhopadhyay , Kaushik Roy, A forward body-biased low-leakage SRAM cache: device and architecture considerations, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea [doi>10.1145/871506.871511]
• 11: C. Kim , K. Roy, Dynamic VTH Scaling Scheme for Active Leakage Power Reduction, Proceedings of the conference on Design, automation and test in Europe, p.163, March 04-08, 2002
• 12: G. Lemieux. Design of interconnection networks for programmable logic devices. In Ph.D. Thesis. Department of Electrical and Computer Engineering, University of Toronto, 2003.
• 13: Guy Lemieux , David Lewis, Circuit design of routing switches, Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays, February 24-26, 2002, Monterey, California, USA [doi>10.1145/503048.503052]
• 14: David Lewis , Vaughn Betz , David Jefferson , Andy Lee , Chris Lane , Paul Leventis , Sandy Marquardt , Cameron McClintock , Bruce Pedersen , Giles Powell , Srinivas Reddy , Chris Wysocki , Richard Cliff , Jonathan Rose, The stratixπ routing and logic architecture, Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays, February 23-25, 2003, Monterey, California, USA [doi>10.1145/611817.611821]
• 15: Steven M. Martin , Krisztian Flautner , Trevor Mudge , David Blaauw, Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.721-725, November 10-14, 2002, San Jose, California [doi>10.1145/774572.774678]
• 16: Siva Narendra , Vivek De , Dimitri Antoniadis , Anantha Chandrakasan , Shekhar Borkar, Scaling of stack effect and its application for leakage reduction, Proceedings of the 2001 international symposium on Low power electronics and design, p.195-200, August 2001, Huntington Beach, California, United States [doi>10.1145/383082.383132]
• 17: M. Nemani and F. N. Najm. High-level area and power estimation for VLSI circuits. IEEE Transactions on Computer Aided Design, 18(6):697--713, June 1999.
• 18: Kara K. W. Poon , Andy Yan , Steven J. E. Wilton, A Flexible Power Model for FPGAs, Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications, p.312-321, September 02-04, 2002
• 19: K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand. Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits. In Proceedings of the IEEE, pages 305--327, February 2003.
• 20: Takayasu Sakurai, Minimizing power across multiple technology and design levels, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.24-27, November 10-14, 2002, San Jose, California [doi>10.1145/774572.774576]
• 21: Li Shang , Alireza S. Kaviani , Kusuma Bathala, Dynamic power consumption in Virtex™-II FPGA family, Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays, February 24-26, 2002, Monterey, California, USA [doi>10.1145/503048.503072]
• 22: Supamas Sirichotiyakul , Tim Edwards , Chanhee Oh , Rajendran Panda , David Blaauw, Duet: an accurate leakage estimation and optimization tool for dual-V_t circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.2, p.79-90, April 2002 [doi>10.1109/92.994980]
• 23: T. Tuan and B. Lai. Leakage power analysis of a 90nm FPGA. In IEEE Custom Integrated Circuits Conference, pages 57--60, 2003.
• 24: Kimiyoshi Usami , Naoyuki Kawabe , Masayuki Koizumi , Katsuhiro Seta , Toshiyuki Furusawa, Automated selective multi-threshold design for ultra-low standby applications, Proceedings of the 2002 international symposium on Low power electronics and design, August 12-14, 2002, Monterey, California, USA [doi>10.1145/566408.566458]
• 25: Xilinx, Inc., San Jose, CA. Spartan-3 FPGA Data Sheet, 2003.
• 26: Xilinx, Inc., San Jose, CA. Virtex II PRO FPGA Data Sheet, 2003.
• 27: Gary K. Yeap, Practical low power digital VLSI design, Kluwer Academic Publishers, Norwell, MA, 1998

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids

General Terms:
Algorithms, Design

Keywords:
FPGAs, field-programmable gate arrays, leakage, low-power design, optimization, power