Exploration of pipelined FPGA interconnect structures

ABSTRACT

In this work, we parameterize and explore the interconnect structure of pipelined FPGAs. Specifically, we explore the effects of interconnect register population, length of registered routing track segments, registered IO terminals of logic units, and the flexibility of the interconnect structure on the performance of a pipelined FPGA. Our experiments with the RaPiD [4] architecture identify tradeoffs that must be made while designing the interconnect structure of a pipelined FPGA. The post-exploration architecture that we found shows a 19% improvement over RaPiD, while the area overhead incurred in placing and routing benchmarks netlists on the post-exploration architecture is 18%.

REFERENCES

• 1: Altera Inc., "Stratix Device Family Features", available at http://www.altera.com.
• 2: Vaughn Betz , Jonathan Rose, FPGA routing architecture: segmentation and buffering to optimize speed and density, Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays, p.59-68, February 21-23, 1999, Monterey, California, United States [doi>10.1145/296399.296428]
• 3: V. Betz and J. Rose, "Circuit Design, Transistor Sizing and Wire Layout of FPGA Interconnect", IEEE Custom Integrated Circuits Conference, pp 171--174, 1999.
• 4: Darren C. Cronquist , Chris Fisher , Miguel Figueroa , Paul Franklin , Carl Ebeling, Architecture Design of Reconfigurable Pipelined Datapaths, Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI, p.23, March 21-24, 1999
• 5: D. C. Cronquist , P. Franklin , S. G. Berg , C. Ebeling, Specifying and Compiling Applications for RaPiD, Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, p.116, April 15-17, 1998
• 6: Carl Ebeling , Darren C. Cronquist , Paul Franklin, RaPiD - Reconfigurable Pipelined Datapath, Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers, p.126-135, September 23-25, 1996
• 7: Larry McMurchie , Carl Ebeling, PathFinder: a negotiation-based performance-driven router for FPGAs, Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays, p.111-117, February 12-14, 1995, Monterey, California, United States [doi>10.1145/201310.201328]
• 8: C. Sechen, VLSI Placement and Global Routing Using Simulated Annealing, Kluwer Academic Publishers, Boston, MA: 1988.
• 9: A. Sharma, "Development of a Place and Route Tool for the RaPiD Architecture", Master's Project, University of Washington, December 2001.
• 10: Akshay Sharma , Carl Ebeling , Scott Hauck, PipeRoute: a pipelining-aware router for FPGAs, Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays, February 23-25, 2003, Monterey, California, USA [doi>10.1145/611817.611829]
• 11: Amit Singh , Arindam Mukherjee , Malgorzata Marek-Sadowska, Interconnect pipelining in a throughput-intensive FPGA architecture, Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays, p.153-160, February 2001, Monterey, California, United States [doi>10.1145/360276.360323]
• 12: Deshanand P. Singh , Stephen D. Brown, The case for registered routing switches in field programmable gate arrays, Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays, p.161-169, February 2001, Monterey, California, United States [doi>10.1145/360276.360331]
• 13: William Tsu , Kip Macy , Atul Joshi , Randy Huang , Norman Walker , Tony Tung , Omid Rowhani , Varghese George , John Wawrzynek , André DeHon, HSRA: high-speed, hierarchical synchronous reconfigurable array, Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays, p.125-134, February 21-23, 1999, Monterey, California, United States [doi>10.1145/296399.296442]
• 14: Xilinx Inc., "VirtexII Platform FPGA Features", available at http://www.xilinx.com.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Gate arrays

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
          Subjects: Placement and routing

General Terms:
Algorithms, Experimentation, Measurement

Keywords:
PipeRoute, architecture explorations, pipelined FPGA, pipelined interconnect, registered routing