Early and accurate analysis of SoCs: oxymoron or real?

ABSTRACT

This presentation discusses the major problems in doing early estimation of various design metrics in systems-on-chip (SoC) design, and explains why early and accurate are usually contradictory terms. It then describes a tool for early estimation and analysis of SoCs which is capable of quickly evaluating cross-domain effects between component selection, architectural decisions, floorplanning, wiring estimation and die size prediction.

REFERENCES

• 1: Reinaldo A. Bergamaschi , Subhrajit Bhattacharya , Ronoldo Wagner , Colleen Fellenz , Michael Muhlada , William R. Lee , Foster White , Jean-Marc Daveau, Automating the Design of SOCs Using Cores, IEEE Design & Test, v.18 n.5, p.32-45, September 2001 [doi>10.1109/54.953270]
• 2: "The CoreConnect™ Bus Architecture", white paper, available from http://www.ibm.com/chips/products/coreconnect/.
• 3: Thorsten Grotker, System Design with SystemC, Kluwer Academic Publishers, Norwell, MA, 2002
• 4: J. A. Darringer , R. A. Bergamaschi , S. Bhattacharya , D. Brand , A. Herkersdorf , J. K. Morrell , I. Nair , P. Sagmeister , Y. Shin, Early analysis tools for system-on-a-chip design, IBM Journal of Research and Development, v.46 n.6, p.691-707, November 2002
• 5: Luca Benini , Robin Hodgson , Polly Siegel, System-level power estimation and optimization, Proceedings of the 1998 international symposium on Low power electronics and design, p.173-178, August 10-12, 1998, Monterey, California, United States [doi>10.1145/280756.280881]

INDEX TERMS

Primary Classification:
  J. Computer Applications
  J.6 COMPUTER-AIDED ENGINEERING

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids

General Terms:
Algorithms

Keywords:
design analysis, design space exploration, floorplanning, performance, power